NUC120LD2BN Nuvoton Technology Corporation of America, NUC120LD2BN Datasheet - Page 200
![IC MCU 32BIT 64KB FLASH 48LQFP](/photos/28/73/287352/nuc120ld2bn_sml.jpg)
NUC120LD2BN
Manufacturer Part Number
NUC120LD2BN
Description
IC MCU 32BIT 64KB FLASH 48LQFP
Manufacturer
Nuvoton Technology Corporation of America
Series
NuMicro™r
Specifications of NUC120LD2BN
Core Processor
ARM Cortex-M0
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, IrDA, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, I²S, LVD, POR, PS2, PWM, WDT
Number Of I /o
31
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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NUC120LD2BN
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NuvoTon
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Company:
Part Number:
NUC120LD2BN
Manufacturer:
Nuvoton Technology Corporation of America
Quantity:
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APB Devices Clock Enable Control Register (APBCLK)
These bits of this register are used to enable/disable clock for peripheral controller clocks.
Register
APBCLK
Bits
[31]
[30]
[29]
[28]
[27]
[26:25]
[24]
[23]
PWM67_EN
Reserved
SPI3_EN
PS2_EN
31
23
15
7
NuMicro™ NUC100 Series Technical Reference Manual
Offset
CLK_BA+0x08
Descriptions
PS2_EN
ACMP_EN
I2S_EN
ADC_EN
USBD_EN
Reserved
CAN0_EN
PWM67_EN
PWM45_EN
ACMP_EN
FDIV_EN
SPI2_EN
30
22
14
6
PWM23_EN
TMR3_EN
SPI1_EN
I2S_EN
R/W
R/W
PS2 Clock Enable
1 = Enable PS2 clock
0 = Disable PS2 clock
Analog Comparator Clock Enable
1 = Enable the Analog Comparator Clock
0 = Disable the Analog Comparator Clock
I2S Clock Enable
1 = Enable I
0 = Disable I
Analog-Digital-Converter (ADC) Clock Enable
1 = Enable ADC clock
0 = Disable ADC clock
USB 2.0 FS Device Controller Clock Enable
1 = Enable USB clock
0 = Disable USB clock
Reserved
CAN Bus Controller-0 Clock Enable
1 = Enable CAN0 clock
0 = Disable CAN0 clock
PWM_67 Clock Enable (Medium Density Only)
1 = Enable PWM67 clock
0 = Disable PWM67 clock
29
21
13
5
Description
APB Devices Clock Enable Control Register
PWM01_EN
2
2
S Clock
TMR2_EN
S Clock
ADC_EN
SPI0_EN
28
20
12
4
- 200 -
USBD_EN
TMR1_EN
Reserved
27
19
11
3
Reserved
Publication Release Date: Dec. 22, 2010
UART2_EN
TMR0_EN
26
18
10
2
Reserved
UART1_EN
I2C1_EN
RTC_EN
25
17
9
1
Revision V1.06
Reset Value
0x0000_000X
UART0_EN
CAN0_EN
WDT_EN
I2C0_EN
24
16
8
0
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