NUC120LC1BN Nuvoton Technology Corporation of America, NUC120LC1BN Datasheet - Page 474
![IC MCU 32BIT 32KB FLASH 48LQFP](/photos/28/73/287345/nuc120lc1bn_sml.jpg)
NUC120LC1BN
Manufacturer Part Number
NUC120LC1BN
Description
IC MCU 32BIT 32KB FLASH 48LQFP
Manufacturer
Nuvoton Technology Corporation of America
Series
NuMicro™r
Specifications of NUC120LC1BN
Core Processor
ARM Cortex-M0
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, IrDA, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, I²S, LVD, POR, PS2, PWM, WDT
Number Of I /o
31
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Manufacturer
Quantity
Price
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Part Number:
NUC120LC1BN
Manufacturer:
Nuvoton Technology Corporation of America
Quantity:
10 000
Part Number:
NUC120LC1BN
Manufacturer:
NUVOTON
Quantity:
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[16]
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NuMicro™ NUC100 Series Technical Reference Manual
LCHZCEN
RCHZCEN
MCLKEN
RXTH[2:0]
TXTH[2:0]
Left channel zero cross detect enable
If this bit is set to 1, when left channel data sign bit change or next shift data bits are all
zero then LZCF flag in I2S_STATUS register is set to 1.
1 = Enable left channel zero cross detect
0 = Disable left channel zero cross detect
Right channel zero cross detect enable
If this bit is set to 1, when left channel data sign bit change or next shift data bits are all
zero then LZCF flag in I2S_STATUS register is set to 1.
1 = Enable right channel zero cross detect
0 = Disable right channel zero cross detect
Master clock enable
If NuMicro™ NUC100 series, external crystal clock is frequency 2*N*256fs then
software can program MCLK_DIV[2:0] in I2S_CLKDIV register to get 256fs clock to
audio codec chip.
1 = Enable master clock
0 = Disable master clock
Receive FIFO threshold level
When received data word(s) in buffer is equal or higher than threshold level then
RXTHI flag is set.
000 = 1 word data in receive FIFO
001 = 2 word data in receive FIFO
010 = 3 word data in receive FIFO
011 = 4 word data in receive FIFO
100 = 5 word data in receive FIFO
101 = 6 word data in receive FIFO
110 = 7 word data in receive FIFO
111 = 8 word data in receive FIFO
Transmit FIFO threshold level
If remain data word (32 bits) in transmit FIFO is the same or less than threshold level
then TXTHI flag is set.
000 = 0 word data in transmit FIFO
001 = 1 word data in transmit FIFO
010 = 2 words data in transmit FIFO
011 = 3 words data in transmit FIFO
100 = 4 words data in transmit FIFO
101 = 5 words data in transmit FIFO
110 = 6 words data in transmit FIFO
111 = 7 words data in transmit FIFO
- 474 -
Publication Release Date: Dec. 22, 2010
Revision V1.06
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