NUC120LC1BN Nuvoton Technology Corporation of America, NUC120LC1BN Datasheet - Page 430
![IC MCU 32BIT 32KB FLASH 48LQFP](/photos/28/73/287345/nuc120lc1bn_sml.jpg)
NUC120LC1BN
Manufacturer Part Number
NUC120LC1BN
Description
IC MCU 32BIT 32KB FLASH 48LQFP
Manufacturer
Nuvoton Technology Corporation of America
Series
NuMicro™r
Specifications of NUC120LC1BN
Core Processor
ARM Cortex-M0
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, IrDA, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, I²S, LVD, POR, PS2, PWM, WDT
Number Of I /o
31
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
NUC120LC1BN
Manufacturer:
Nuvoton Technology Corporation of America
Quantity:
10 000
Part Number:
NUC120LC1BN
Manufacturer:
NUVOTON
Quantity:
20 000
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COMMAND Register (COMMAND)
Register
COMMAND
Bits
[31:9]
[8]
[7]
[6]
[5:2]
[1]
CAN_EN
31
23
15
7
NuMicro™ NUC100 Series Technical Reference Manual
Offset
CAN0_BA+0x04
WAKEUP_EN
Descriptions
Reserved
HW_SYNC
CAN_EN
WAKEUP_EN
Reserved
ABRT
30
22
14
6
R/W
R/W
Reserved
Hardware Synchronization
It is used to define the time quantum offset is calculated by hardware or configured by
the parameter of SJW which defined in the BTIMR register.
1 = Enable the hardware synchronization.
The bit timing synchronization is done by hardware and the time quantum offset is
calculated automatically by internal hardware design.
0 = Disable the hardware synchronization.
The time quantum offset for the bit timing synchronization is configured in the
parameter of SJW which defined in BTIMR register.
Note: the time quantum offset is used to compensate the propagation delay or phased
shifts of CAN bus line.
CAN Controller Enable
1 = Enable the CAN controller
0 = Disable the CAN controller
WAKE UP Enable
1 = Enable the wake up function
It will enable the wake up function when the system is in sleep mode.
As the received signal (RX) toggle from ‘recessive’ to ‘dominant’ on the CAN Bus and
the WAKEUP_EN bit is set to 1, it will wake up the system.
0 = Disable the wake up function
Note: When the system had been wake up, this bit must be clear before the user clears
the interrupt flag WUI.
Reserved
Abort Automatic Re-Transmission
1 = Abort automatic re-transmission after a message transmission failure
29
21
13
5
Description
Command Register
Reserved
28
20
12
4
- 430 -
Reserved
Reserved
Reserved
27
19
11
3
Publication Release Date: Dec. 22, 2010
26
18
10
2
ABRT
25
17
9
1
Revision V1.06
Reset Value
0x0000_0100
HW_SYNC
TXREQ
24
16
8
0
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