NUC120LC1BN Nuvoton Technology Corporation of America, NUC120LC1BN Datasheet - Page 211
![IC MCU 32BIT 32KB FLASH 48LQFP](/photos/28/73/287345/nuc120lc1bn_sml.jpg)
NUC120LC1BN
Manufacturer Part Number
NUC120LC1BN
Description
IC MCU 32BIT 32KB FLASH 48LQFP
Manufacturer
Nuvoton Technology Corporation of America
Series
NuMicro™r
Specifications of NUC120LC1BN
Core Processor
ARM Cortex-M0
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, IrDA, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, I²S, LVD, POR, PS2, PWM, WDT
Number Of I /o
31
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
NUC120LC1BN
Manufacturer:
Nuvoton Technology Corporation of America
Quantity:
10 000
Part Number:
NUC120LC1BN
Manufacturer:
NUVOTON
Quantity:
20 000
- NUC100LC1BN PDF datasheet
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- Download datasheet (6Mb)
Clock Divider Register (CLKDIV)
Register
CLKDIV
Bits
[31:30]
[29:24]
[23:16]
[15:12]
[11:8]
[7:4]
[3:0]
31
23
15
7
Reserved
NuMicro™ NUC100 Series Technical Reference Manual
Offset
CLK_BA+0x18
Descriptions
Reserved
CAN_N_H
ADC_N
CAN_N_L
UART_N
USB_N
HCLK_N
30
22
14
6
CAN_N_L
USB_N
R/W
R/W
Reserved
CAN clock divide number from CAN clock source (Low Density Only)
The CAN clock frequency = (CAN clock source frequency ) / (CAN_N + 1)
Which CAN_N = 16 * CAN_N_H + CAN_N_L
ADC clock divide number from ADC clock source
The ADC clock frequency = (ADC clock source frequency ) / (ADC_N + 1)
CAN clock divide number from CAN clock source
The CAN clock frequency = (CAN clock source frequency ) / (CAN_N + 1)
Which CAN_N = 16 * CAN_N_H + CAN_N_L
UART clock divide number from UART clock source
The UART clock frequency = (UART clock source frequency ) / (UART_N + 1)
USB clock divide number from PLL clock
The USB clock frequency = (PLL frequency ) / (USB_N + 1)
HCLK clock divide number from HCLK clock source
The HCLK clock frequency = (HCLK clock source frequency) / (HCLK_N + 1)
29
21
13
5
Description
Clock Divider Number Register
28
20
12
4
- 211 -
ADC_N
27
19
11
3
CAN_N_H
Publication Release Date: Oct 22, 2010
26
18
10
2
UART_N
HCLK_N
25
17
9
1
Revision V1.06
Reset Value
0x0000_0000
24
16
8
0
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