XRT75R03IVTR Exar Corporation, XRT75R03IVTR Datasheet - Page 83

• Manufacturer Part Number: XRT75R03IVTR
• Description: IC LIU E3/DS3/STS-1 3CH 128LQFP
• Manufacturer: Exar Corporation

Specifications of XRT75R03IVTR

• Lead Free Status / RoHS Status: Contains lead / RoHS Compliant

xr
xr
xr
xr
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
B
IT
7 - 6
N
B
R/O
UMBER
5
IT
0
7
Unused
T
ABLE
PRBS Enable
B
R/O
Unused
IT
0
N
29: C
AME
6
HANNEL
PRBS Enable
Ch_n
B
R/W
IT
0
C
5
ONTROL
T
R/W
R/O
YPE
R
RLB_n
B
R/W
EGISTER
D
IT
0
V
EFAULT
ALUE
4
0
0
Channel 1 Address Location = 0x0E
Channel 2 Address Location = 0x16
80
- C
PRBS Generator and Receiver Enable - Channel_n:
This READ/WRITE bit-field is used to either enable or dis-
able the PRBS Generator and Receiver within a given
Channel of the XRT75R03.
If the user enables the PRBS Generator and Receiver,
then the following will happen.
0 - Disables both the PRBS Generator and PRBS Receiver
within the corresponding channel.
1 - Enables both the PRBS Generator and PRBS Receiver
within the corresponding channel.
N
HANNEL
OTES
LLB_n
B
1. The PRBS Generator (which resides within the
2. The PRBS Receiver (which resides within the
R/W
IT
0
1. To check and monitor PRBS Bit Errors, Bit 0 (SR/
2. If the user enables the PRBS Generator and
3. Use of the PRBS Generator and Receiver is only
Transmit Section of the Channel) will begin to
generate an unframed, 2^15-1 PRBS Pattern (for
DS3 and STS-1 applications) and an unframed,
2^23-1 PRBS Pattern (for E3 applications).
Receive Section of the Channel) will now be
enabled and will begin to search the incoming data
for the above-mentioned PRBS patterns.
:
3
DR_n) within this register Must be set to "0". This
step will configure the RNEG_n/LCV_n output pin
to function as the PRBS Error Indicator. In this
case, external glue logic will be needed to monitor
and count the number of PRBS Bit Errors that are
detected by the PRBS Receiver.
PRBS Receiver, then the Channel will ignore the
data that is being accepted from the System-side
Equipment (via the TPDATA_n and TNDATA_n
input pins) and will overwrite this outbound data
with the PRBS Pattern.
available through the Host Mode.
0 A
DDRESS
E3_n
B
R/W
IT
0
2
D
L
ESCRIPTION
OCATION
STS-1/DS3_n
B
R/W
= 0
IT
0
1
X
06
XRT75R03
SR/DR_n
REV. 1.0.8
B
R/W
IT
0
0