MFRC52301HN1,151 NXP Semiconductors, MFRC52301HN1,151 Datasheet - Page 93

• Manufacturer Part Number: MFRC52301HN1,151
• Description: IC MIFARE READER 32-HVQFN
• Manufacturer: NXP Semiconductors
• Series: MIFARE®r

Specifications of MFRC52301HN1,151

• Frequency: 13.56MHz
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Operating Current: 7 mA
• Operating Voltage: 2.5 V to 3.6 V
• Product: RFID Readers
• Wireless Frequency: 13.56 MHz
• Interface Type: RS-232, I2C
• Data Rate: 100 Kbps
• Operating Temperature Range: - 25 C to +85 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Rf Type: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-4766; 935282956151; MFRC52301HN1

NXP Semiconductors
Table 69. RxThresholdReg register bit descriptions . . . .50
Table 70. DemodReg register (address 19h);
Table 71. DemodReg register bit descriptions . . . . . . . . .50
Table 72. Reserved register (address 1Ah);
Table 73. Reserved register bit descriptions . . . . . . . . . .51
Table 74. Reserved register (address 1Bh);
Table 75. Reserved register bit descriptions . . . . . . . . . .51
Table 76. MfTxReg register (address 1Ch);
Table 77. MfTxReg register bit descriptions . . . . . . . . . .52
Table 78. MfRxReg register (address 1Dh);
Table 79. MfRxReg register bit descriptions . . . . . . . . . .52
Table 80. TypeBReg register (address 1Eh);
Table 81. TypeBReg register bit descriptions . . . . . . . . .52
Table 82. SerialSpeedReg register (address 1Fh);
Table 83. SerialSpeedReg register bit descriptions . . . . .53
Table 84. Reserved register (address 20h);
Table 85. Reserved register bit descriptions . . . . . . . . . .54
Table 86. CRCResultReg (higher bits) register
Table 87. CRCResultReg register higher
Table 88. CRCResultReg (lower bits) register
Table 89. CRCResultReg register lower bit descriptions .54
Table 90. Reserved register (address 23h);
Table 91. Reserved register bit descriptions . . . . . . . . . .55
Table 92. ModWidthReg register (address 24h);
Table 93. ModWidthReg register bit descriptions . . . . . .55
Table 94. Reserved register (address 25h);
Table 95. Reserved register bit descriptions . . . . . . . . . .55
Table 96. RFCfgReg register (address 26h);
Table 97. RFCfgReg register bit descriptions . . . . . . . . .56
Table 98. GsNReg register (address 27h);
Table 99. GsNReg register bit descriptions . . . . . . . . . . .56
Table 100. CWGsPReg register (address 28h);
MFRC523_34
Product data sheet
PUBLIC
reset value: 84h bit allocation . . . . . . . . . . . . .50
reset value: 4Dh bit allocation . . . . . . . . . . . . .50
reset value: 00h bit allocation . . . . . . . . . . . . .51
reset value: 00h bit allocation . . . . . . . . . . . . .51
reset value: 62h bit allocation . . . . . . . . . . . . .51
reset value: 00h bit allocation . . . . . . . . . . . . .52
reset value: 00h bit allocation . . . . . . . . . . . . .52
reset value: EBh bit allocation . . . . . . . . . . . . .53
reset value: 00h bit allocation . . . . . . . . . . . . .54
(address 21h); reset value:
FFh bit allocation . . . . . . . . . . . . . . . . . . . . . . .54
bit descriptions . . . . . . . . . . . . . . . . . . . . . . . . .54
(address 22h); reset value:
FFh bit allocation . . . . . . . . . . . . . . . . . . . . . . .54
reset value: 88h bit allocation . . . . . . . . . . . . .55
reset value: 26h bit allocation . . . . . . . . . . . . .55
reset value: 87h bit allocation . . . . . . . . . . . . .55
reset value: 48h bit allocation . . . . . . . . . . . . .56
reset value: 88h bit allocation . . . . . . . . . . . . .56
All information provided in this document is subject to legal disclaimers.
Rev. 3.5 — 24 September 2010
115235
Table 101. CWGsPReg register bit descriptions . . . . . . . 57
Table 102. ModGsPReg register (address 29h);
Table 103. ModGsPReg register bit descriptions . . . . . . . 57
Table 104. TModeReg register (address 2Ah);
Table 105. TModeReg register bit descriptions . . . . . . . . 58
Table 106. TPrescalerReg register (address 2Bh);
Table 107. TPrescalerReg register bit descriptions . . . . . 59
Table 108. TReloadReg (higher bits) register
Table 109. TReloadReg register higher bit descriptions . 59
Table 110. TReloadReg (lower bits) register
Table 111. TReloadReg register lower bit descriptions . . 59
Table 112. TCounterValReg (higher bits) register
Table 113. TCounterValReg register higher
Table 114. TCounterValReg (lower bits) register
Table 115. TCounterValReg register lower
Table 116. Reserved register (address 30h);
Table 117. Reserved register bit descriptions . . . . . . . . . 60
Table 118. TestSel1Reg register (address 31h);
Table 119. TestSel1Reg register bit descriptions . . . . . . . 60
Table 120. TestSel2Reg register (address 32h);
Table 121. TestSel2Reg register bit descriptions . . . . . . . 61
Table 122. TestPinEnReg register (address 33h);
Table 123. TestPinEnReg register bit descriptions . . . . . 61
Table 124. TestPinValueReg register (address 34h);
Table 125. TestPinValueReg register bit descriptions . . . 62
Table 126. TestBusReg register (address 35h);
Table 127. TestBusReg register bit descriptions . . . . . . . 62
Table 128. AutoTestReg register (address 36h);
Table 129. AutoTestReg register bit descriptions . . . . . . . 63
Table 130. VersionReg register (address 37h);
Table 131. VersionReg register bit descriptions . . . . . . . . 63
Table 132. AnalogTestReg register (address 38h);
reset value: 20h bit allocation . . . . . . . . . . . . . 57
reset value: 20h bit allocation . . . . . . . . . . . . . 57
reset value: 00h bit allocation . . . . . . . . . . . . . 57
reset value: 00h bit allocation . . . . . . . . . . . . . 58
(address 2Ch); reset value: 00h bit allocation . 59
(address 2Dh); reset value: 00h bit allocation . 59
(address 2Eh); reset value: xxh bit allocation . 59
bit descriptions . . . . . . . . . . . . . . . . . . . . . . . . 60
(address 2Fh); reset value: xxh bit allocation . 60
bit descriptions . . . . . . . . . . . . . . . . . . . . . . . . 60
reset value: 00h bit allocation . . . . . . . . . . . . . 60
reset value: 00h bit allocation . . . . . . . . . . . . . 60
reset value: 00h bit allocation . . . . . . . . . . . . . 61
reset value: 80h bit allocation . . . . . . . . . . . . . 61
reset value: 00h bit allocation . . . . . . . . . . . . . 62
reset value: xxh bit allocation . . . . . . . . . . . . . 62
reset value: 40h bit allocation . . . . . . . . . . . . . 62
reset value: xxh bit allocation . . . . . . . . . . . . . 63
reset value: 00h bit allocation . . . . . . . . . . . . . 63
Contactless reader IC
MFRC523
© NXP B.V. 2010. All rights reserved.
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