MFRC52301HN1,151 NXP Semiconductors, MFRC52301HN1,151 Datasheet - Page 50

• Manufacturer Part Number: MFRC52301HN1,151
• Description: IC MIFARE READER 32-HVQFN
• Manufacturer: NXP Semiconductors
• Series: MIFARE®r

Specifications of MFRC52301HN1,151

• Frequency: 13.56MHz
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Operating Current: 7 mA
• Operating Voltage: 2.5 V to 3.6 V
• Product: RFID Readers
• Wireless Frequency: 13.56 MHz
• Interface Type: RS-232, I2C
• Data Rate: 100 Kbps
• Operating Temperature Range: - 25 C to +85 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Rf Type: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-4766; 935282956151; MFRC52301HN1

NXP Semiconductors
MFRC523_34
Product data sheet
PUBLIC
9.2.2.10 DemodReg register
9.2.2.9 RxThresholdReg register
Selects thresholds for the bit decoder.
Table 68.
Table 69.
Defines demodulator settings.
Table 70.
Table 71.
Bit
Symbol
Access
Bit
7 to 4
3
2 to 0
Bit
Symbol
Access
Bit
7 to 6
5
Symbol
AddIQ[1:0]
FixIQ
Symbol
MinLevel[3:0]
reserved
CollLevel[2:0]
RxThresholdReg register (address 18h); reset value: 84h bit allocation
RxThresholdReg register bit descriptions
DemodReg register (address 19h); reset value: 4Dh bit allocation
DemodReg register bit descriptions
7
7
AddIQ[1:0]
All information provided in this document is subject to legal disclaimers.
R/W
Rev. 3.5 — 24 September 2010
Value
-
00
01
10
11
1
MinLevel[3:0]
6
6
Description
defines the minimum signal strength at the decoder input that will be
accepted. If the signal strength is below this level it is not evaluated
reserved for future use
defines the minimum signal strength at the decoder input that must be
reached by the weaker half-bit of the Manchester encoded signal to
generate a bit-collision relative to the amplitude of the stronger half-bit
R/W
115235
Description
defines the use of I-channel and Q-channel during reception
Remark: the FixIQ bit must be set to logic 0 to enable the
following settings:
if the bits of AddIQ are set to X0, the reception is fixed to
I-channel
if the bits of AddIQ are set to X1, the reception is fixed to
Q-channel
FixIQ
R/W
selects the stronger channel
selects the stronger channel and freezes the selected channel
during communication
reserved
reserved
5
5
TPrescal
Even
4
4
-
reserved
3
3
-
TauRcv[1:0]
R/W
2
2
Contactless reader IC
CollLevel[2:0]
MFRC523
© NXP B.V. 2010. All rights reserved.
R/W
TauSync[1:0]
1
1
R/W
50 of 97
0
0