AS3977-BQFT austriamicrosystems, AS3977-BQFT Datasheet - Page 23

• Manufacturer Part Number: AS3977-BQFT
• Description: IC RF TRANSMITTER FSK 16-QFN
• Manufacturer: austriamicrosystems

Specifications of AS3977-BQFT

• Frequency: 300MHz ~ 928MHz
• Applications: ISM
• Modulation Or Protocol: FSK
• Data Rate - Maximum: 100 kbps
• Power - Output: 10dBm
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Voltage - Supply: 2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-VQFN Exposed Pad, 16-HVQFN, 16-SQFN, 16-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Memory Size: -
• Current - Transmitting: -

AS3977
Data Sheet - A p p l i c a t i o n I n f o r m a t i o n
Figure 9. Writing of Data with Auto-Incrementing Address
Reading of Data from Addressable Registers
By leaving the Power Down Mode through a rising edge of ENABLE, the level of CLK determines the sampling edge of
CLK. If CLK is low, DATAI is sampled at the falling edge of CLK (see
ENABLE rises, DATAI is sampled at the rising edge of CLK. Consequently, data to be read from the microcontroller are
driven by the slave (AS3977) at the transfer edge and sampled by the master (µC) at the sampling edge of CLK. An
Enable LOW pulse has to be performed after register data has been transferred in order to indicate the end of the
READ command and prepare the Interface to the next command control Byte.
The command control Byte for a read command consists of a command code and an address. The Command code
has to be provided from least significant bit (LSB) to most significant bit (MSB), e.g. for a read it is <C0, C1> = “01”.
After the command code, the address of register to be read has to be provided from the MSB to the LSB. Then one or
more data bytes can be transferred from the SDI slave to the master, always from the MSB to the LSB. To transfer
bytes from consecutive addresses, SDI master has to keep the SDI enable signal high and the SDI clock has to be
active as long as data need to be read from the slave.
Each bit of the command and address sections of the frame have to be driven by the SDI master on the SDI clock
transfer edge and the SDI slave samples it on the next SDI clock edge. Each bit of the data section of the frame has to
be driven by the SDI slave on the SDI clock transfer edge and the SDI master on the next SDI clock edge samples it.
These edges are selected on the first access after PD and they cannot be changed until next PD.
If the read access is interrupted (by de-asserting the SDI enable signal), data provided to the master is consistent to
given address, but it is only the register content from MSB to LSB. If more SDI clock cycles are provided, data remains
consistent and each data byte belongs to given or incremented address.
In the following figures
increment) are given. The initialization base for this timing diagram is a “LOW” on the CLK line during Initialization.
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ENABLE
DATAIO
CLK
0
0
A
5
A
4
(Figure 10
A
3
A
2
A
1
A
0
D
7
D
6
and
D
5
D
4
Figure
D
3
Data D7-D0
is moved to
A5-A0 here
D
2
Address
D
1
D
0
11), two examples for a read command (without and with address self-
D
7
D
6
D
5
D
4
Revision 3.5
D
3
Data D7-D0
is moved to
D
2
A5-A0+1
Address
D
1
here
D
0
D
7
D
6
D
5
Figure 10
D
4
D
3
Data D7-D0
is moved to
D
2
A5-A0+2
Address
D
1
here
D
0
and
D
7
D
6
D
5
Figure
D
4
D
3
Data D7-D0
D
is moved to
2
A5-A0+3
Address
11), if CLK is high when
D
1
here
D
0
D
7
D
6
D
5
Enable must be
keep the power
high in order to
D
4
D
3
condition
Data D7-D0
D
2
is moved to
A5-A0+4
Address
D
1
here
D
0
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