AS3977-BQFT austriamicrosystems, AS3977-BQFT Datasheet - Page 21

• Manufacturer Part Number: AS3977-BQFT
• Description: IC RF TRANSMITTER FSK 16-QFN
• Manufacturer: austriamicrosystems

Specifications of AS3977-BQFT

• Frequency: 300MHz ~ 928MHz
• Applications: ISM
• Modulation Or Protocol: FSK
• Data Rate - Maximum: 100 kbps
• Power - Output: 10dBm
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Voltage - Supply: 2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-VQFN Exposed Pad, 16-HVQFN, 16-SQFN, 16-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Memory Size: -
• Current - Transmitting: -

AS3977
Data Sheet - A p p l i c a t i o n I n f o r m a t i o n
Configuration Diagram
The interface has one clock signal for the external µC and the SDI input clock. As the MCCLK line can be used to clock
the SDI Interface as well as must have a high impedance pin during the clocking phase of the microcontroller, the Pin
must be bi-directional. The pad behavior is selected by configuration bits and by setting the SDI DATA-IO Line of the
SDI interface when leaving PD. Possible configurations between the interface and the µC are done using 4 wires as
shown in
MCCLK is simply connected to the micro controller and can be used to clock a timer or interrupt logic.
Figure 7. Configuration Diagram
A connection using a set of three wires is required to implement the SDI protocol.
The interface supports the following functionality for the micro controller clock output (MCCLK).
The rising edge of ENABLE after a Power Down Mode selects the transfer edge of the SDI-CLK by sampling the SDI
clock value itself. This configuration will be valid until the next PD. Each bit must be transferred and sampled according
to the configured edges. For example, if at the first rising edge of SDI enable SDI clock is LOW, then each bit is
transferred from the microcontroller on the rising edge of SDI clock and it is sampled from AS3977 on falling edge of
the SDI clock. This is valid for read as well as for write commands.
During the first byte of the WRITE command communication (command and address), the SDI master drives each new
data bit on the transfer active edge and the SDI slave samples it on the next opposite edge. This protocol will be valid
until the last data bit has been written to the external registers. Data’ are transferred to the registers byte by byte after
sampling of the last bit.
It is not necessary to enter the PD mode for reset the Interface. The rising edge of SDI-ENABLE signal starts the
communication.
When the command is READ, a direction change on the SDI data wire will be done. This change has to be performed
synchronously on SDI master and slave side, however, the master always provide the SDI clock. After sampling the
last addressed bit, the SDI slave pin becomes active on the following SDI clock edge and the first readable bit read is
transferred from SDI slave to the master.
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ENABLE signal is used to activate the interface and to wake up the whole IC. In addition, the rising edge of the
ENABLE after power down mode is used to set the starting point of the communication protocol.
CLK represents the SDI clock and both edges can be used for data transfer, dependable on the configuration after
wake-up.
DATAIO is a bi-directional signal that goes from microcontroller to the Interface during write and transmit-
commands, while it is in the other direction when the interface is sending data read from the micro controller.
MCCLK can be inactive (MCCLK level not defined), always active after start-up (MCCLK is clocking) or clocking
only during transmit.
It is possible to configure and to maintain MCCLK settings (even when leaving PD).
Maximum frequency is specified to f
Minimum frequency is f
and timer counter value of 255).
Figure
7.
µC
XOSC
/ 65280 (by using the baud rate generator output with prescaler division ratio of 128
XOSC
(by using the prescaler output with a division ratio of 1, PSC=0).
Revision 3.5
ENABLE
DATAIO
MCCLK
CLK
AS3977
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