SX1223I073TRT Semtech, SX1223I073TRT Datasheet - Page 11

• Manufacturer Part Number: SX1223I073TRT
• Description: IC TX UHF 433/868/916 MHZ 24TQFN
• Manufacturer: Semtech

Specifications of SX1223I073TRT

• Frequency: 425 ~ 475MHz / 850 ~ 950MHz
• Applications: AMR, Home Automation, HQ Music and Data
• Modulation Or Protocol: FSK
• Data Rate - Maximum: 153.6 kbps
• Power - Output: 10dBm
• Current - Transmitting: 25.8mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Voltage - Supply: 2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 24-TQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Memory Size: -
• Other names: SX1223I073TR

4.1.6
4.2.1
4.2.2
A lock detector can be enabled by setting LD_en=1. When enabled pin LD is set high, indicating that the PLL is in
lock. The lock detect signal can also be used to control the PA; if LD is low the PA is turned off and vice versa. To
enable this function, the PA_LDc_en must be set to ‘1’ (see section 4.3).
Care must be taken when monitoring the LD during data transmission using the closed loop modulation. The LD
may show that the PLL is not locked, especially when the loop filter bandwidth is too high relative to the bit rate.
4.2
The modulator has a high degree of flexibility, and there are thus several values that need programming. First, the
settings concerning the data bit rate must be determined, then these values will be used in the calculation of the
frequency deviation. Finally the user must check that the modulator won’t saturate with the values chosen.
The "data interface" can be programmed to synchronous or asynchronous mode (see Table 4).
In asynchronous mode only the DATAIN pin is used for transmitting the data to the SX1223.
In synchronous mode the SX1223 is defined as "Master" and provides a data clock on pin DCLK that allows the
user to utilize low cost micro controller reference frequency. The data interface is defined in such a way that all user
actions should take place on falling edges of DCLK as illustrated in Figure 6. The data are sampled by the SX1223
on the rising edges of DCLK.
Before entering into transmit mode (mw1 or mw2), it is important to set DATAIN to high impedance. The data is
provided directly to the modulation circuit and violation of this may cause abnormal behavior.
© Semtech 2007
MODULATOR
Lock Detect
Introduction
Data Interface
Figure 5
Sync_en
CPO UT, pin 20
Figure 6:
: Loop filter for a) closed loop modulation and b) open loop modulation
0
1
C1
DATAIN
DCLK
Time diagram of the data interface in synchronous mode
C2
State
DataClk pin off
DataClk pin on.
R1
a)
R2
C3
Table 4: Synchronizer mode
VARIN, pin 21
Comments
Transparent transmission of data
Bit-clock is generated by transmitter
11
CPO UT, pin 20
C1
C2
R1
b)
47nF
VARIN, pin 21
C3
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SX1223