SX1223I073TRT Semtech, SX1223I073TRT Datasheet - Page 10

• Manufacturer Part Number: SX1223I073TRT
• Description: IC TX UHF 433/868/916 MHZ 24TQFN
• Manufacturer: Semtech

Specifications of SX1223I073TRT

• Frequency: 425 ~ 475MHz / 850 ~ 950MHz
• Applications: AMR, Home Automation, HQ Music and Data
• Modulation Or Protocol: FSK
• Data Rate - Maximum: 153.6 kbps
• Power - Output: 10dBm
• Current - Transmitting: 25.8mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Voltage - Supply: 2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 24-TQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Memory Size: -
• Other names: SX1223I073TR

4.1.4
4.1.5
The charge pump current can be set to either 125 or 500 A by the CP_HI bit. The default value at power-up is 125
applications
frequency and a high PLL bandwidth, 500 A may provide a better solution.
The design of the PLL filter will strongly affect the performance of the frequency synthesizer. The PLL filter is kept
external for flexibility. The parameters to be considered when designing the loop filter for the SX1223 are primarily
the modulation mode and bit rate. These will also affect the switching time and phase noise.
The frequency modulation can be done in three different ways with the SX1223, either by closed-, open loop VCO
modulation or by modulation with the internal dividers, see Table 3 and modulation selection guide in Table 35.
In closed loop VCO modulation (mw1), the PLL bandwidth needs to be sufficiently low (≈ Bit Rate / 20), so as to
prevent the VCO tracking the modulation and cancelling the modulation.
Using the dividers in mw3 mode, the PLL needs to lock on a new carrier frequency for every new data bit. Now the
PLL bandwidth needs to be sufficiently high (≈ Bit Rate / 2). It may be necessary to implement a third order filter to
futher suppress the phase detector frequency spurs,
For the open loop VCO modulation case (mw2), the PLL bandwidth can be large, as the PLL is deactivated during
the transmission burst and there is no requirement to supress the phase detector frequency
To increase the transmission time in the open loop case, a capacitor of 47 nF can be connected on pin VARIN to
ground (NPO type is advised if the transmission duration is critical). The internal opamp must be enabled to drive
this capacitor, by setting the bit OL_opamp_en to 1.
A schematic for a third order loop filter is shown in Figure 5a. For a second order filter, C3 is not connected and R2
is set to 0
pF must be taken into consideration. Figure 5b shows the loop filter configuration for the open loop VCO modulation
case.
© Semtech 2007
A (CP_HI = ‘0’). The choice of this current affects the loop filter component values (see section 4.1.5). For most
SX1223
SX1223
XCO
XCO
PCB
PCB
Modulation1 Modulation0 State
Charge Pump
Loop Filter
M
M
Modulation mw1
. When designing a third order loop filter, the internal capacitance on the VARIN pin of approximately 6
PFD
PFD
0
0
1
1
the lowest current mode is recommended. For those applications using a high phase detector
R1
R1
C2
20
20
N,A
N,A
0
1
0
1
21
21
2
2
C3
VCO
VCO
MOD
MOD
Closed loop VCO-modulation (mw1)
Open loop VCO-modulation (mw2)
Modulation by A,M and N (mw3)
Not used
SX1223
SX1223
PCB
PCB
XCO
XCO
Figure 4
Table 3: Modulation modes
M
M
Modulation mw2
PFD
PFD
:
Modulation modes
10
C2
R1
R1
20
20
OL opamp
OL opamp
C1
N,A
N,A
21
21
2
2
C3
C3
MOD
MOD
VCO
VCO
Comments
VCO is phase-locked
VCO is free-running
Modulation inside PLL
SX1223
SX1223
XCO
XCO
PCB
PCB
MOD
MOD
M
M
Modulation mw3
PFD
PFD
R1
R1
C2
20
20
www.semtech.com
N,A
N,A
SX1223
C1
R2
R2
21
21
2
2
C3
C3
VCO
VCO