ATZB-24-A2 Atmel, ATZB-24-A2 Datasheet - Page 57

• Manufacturer Part Number: ATZB-24-A2
• Description: KIT MOD 802.15.4/ZIGB 2.4GHZ ANT
• Manufacturer: Atmel

Specifications of ATZB-24-A2

• Frequency: 2.4GHz
• Data Rate - Maximum: 250kbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: Home/Building Automation, Industrial Control and Monitoring
• Power - Output: 3dBm
• Sensitivity: -101dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 19mA
• Current - Transmitting: 18mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kBytes Flash, 8kBytes RAM, 4kBytes EEPROM
• Antenna Connector: On-Board, Chip
• Operating Temperature: -40°C ~ 85°C
• Package / Case: Module
• Tool Type: Wireless Development Kit
• Core Architecture: AVR
• Cpu Core: AVR 8
• Data Bus Width: 8 bit
• Description/function: ZigBit 2.4 GHz Dual Chip Antenna
• Wireless Frequency: 2.4 GHz
• Interface Type: UART, I2C, SPI
• Operating Voltage: 1.8 V to 3.6 V
• Output Power: 3 dBm
• Antenna: Chip Antenna
• Operating Temperature Range: - 40 C to + 85 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8069Q–AVR–12/10
Mnemonics
ROL
ROR
ASR
SWAP
BSET
BCLR
SBI
CBI
BST
BLD
SEC
CLC
SEN
CLN
SEZ
CLZ
SEI
CLI
SES
CLS
SEV
CLV
SET
CLT
SEH
CLH
BREAK
NOP
SLEEP
WDR
Operands
Rd
Rd
Rd
Rd
s
s
A, b
A, b
Rr, b
Rd, b
Description
Rotate Left Through Carry
Rotate Right Through Carry
Arithmetic Shift Right
Swap Nibbles
Flag Set
Flag Clear
Set Bit in I/O Register
Clear Bit in I/O Register
Bit Store from Register to T
Bit load from T to Register
Set Carry
Clear Carry
Set Negative Flag
Clear Negative Flag
Set Zero Flag
Clear Zero Flag
Global Interrupt Enable
Global Interrupt Disable
Set Signed Test Flag
Clear Signed Test Flag
Set Two’s Complement Overflow
Clear Two’s Complement Overflow
Set T in SREG
Clear T in SREG
Set Half Carry Flag in SREG
Clear Half Carry Flag in SREG
Break
No Operation
Sleep
Watchdog Reset
Notes:
1. Cycle times for Data memory accesses assume internal memory accesses, and are not valid
2. One extra cycle must be added when accessing Internal SRAM.
for accesses via the external RAM interface.
MCU Control Instructions
(See specific descr. for BREAK)
(see specific descr. for Sleep)
(see specific descr. for WDR)
SREG(s)
SREG(s)
I/O(A, b)
I/O(A, b)
Rd(n+1)
Rd(3..0)
Rd(0)
Rd(7)
Rd(n)
Rd(n)
Rd(b)
Operation
C
C
C
C
N
N
H
H
T
Z
Z
S
S
V
V
T
T
I
I
←
←
←
←
←
←
←
↔
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
C,
Rd(n),
Rd(7)
C,
Rd(n+1),
Rd(0)
Rd(n+1), n=0..6
Rd(7..4)
1
0
1
0
Rr(b)
T
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
XMEGA A4
Flags
Z,C,N,V,H
Z,C,N,V
Z,C,N,V
None
SREG(s)
SREG(s)
None
None
T
None
C
C
N
N
Z
Z
I
I
S
S
V
V
T
T
H
H
None
None
None
None
#Clocks
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
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