ATMEGA256RZAV-8AU Atmel, ATMEGA256RZAV-8AU Datasheet - Page 71

• Manufacturer Part Number: ATMEGA256RZAV-8AU
• Description: MCU ATMEGA2561/AT86RF230 64-TQFP
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA256RZAV-8AU

• Frequency: 2.4GHz
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: ISM, ZigBee™
• Power - Output: 3dBm
• Sensitivity: -101dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 15.5mA
• Current - Transmitting: 16.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 256kB Flash, 4kB EEPROM, 8kB RAM
• Antenna Connector: PCB, Surface Mount
• Package / Case: 64-TQFP
• Wireless Frequency: 2.4 GHz
• Interface Type: JTAG, SPI
• Output Power: 3 dBm
• For Use With: ATAVRISP2 - PROGRAMMER AVR IN SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Data Rate - Maximum: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: ATmega256

9.7 Frequency Synthesizer (PLL)
9.7.1 Overview
9.7.2 RF Channel Selection
9.7.3 Calibration Loops
5131E-MCU Wireless-02/09
The main PLL features are:
• Generate RX/TX frequencies for all IEEE 802.15.4 - 2.4 GHz channels
• Fully integrated fractional-N synthesizer
• Autonomous calibration loops for stable operation within the operating range
• Two PLL-interrupts for status indication
The synthesizer of the AT86RF230 is implemented as a fractional-N PLL. The PLL is
fully integrated and configurable by registers 0x08 (PHY_CC_CCA), 0x1A (PLL_CF)
and 0x1B (PLL_DCU).
The PLL is turned on when entering the state PLL_ON and stays on in all receive and
transmit states. The PLL settles to the correct frequency needed for RX or TX operation
according to the adjusted channel center frequency in register 0x08 (PHY_CC_CCA).
Two calibration loops ensure correct PLL functionality within the specified operating
limits.
The PLL is designed to support 16 channels in the IEEE 802.15.4 – 2.4 GHz band with
a channel spacing of 5 MHz. The center frequency F
follows:
F
where k is the channel number.
The channel k is selected by register bits CHANNEL (register 0x08, PHY_CC_CA).
The center frequency control loop ensures a correct center frequency of the VCO for
the currently programmed channel.
The delay calibration unit compensates the phase errors inherent in fractional-N PLLs.
Using this technique, unwanted spurious frequency components beside the RF carrier
are suppressed, and the PLL behaves similar to an integer-N PLL.
Both calibration routines are initiated automatically when the PLL is turned on.
Additionally, the center frequency calibration is running when the PLL is programmed to
a different channel (register bits CHANNEL in register 0x08).
If the PLL operates for a long time on the same channel or the operating temperature
changes significantly, the control loops should be initiated manually. The recommended
calibration interval is 5 min.
Both calibration loops can be initiated manually by setting PLL_CF_START = 1 of
register 0x1A (PLL_CF) and register bit PLL_DCU_START = 1 of register 0x1B
Register Bit
CH
= 2405 + 5 (k – 11) [MHz], for k = 11, 12, ..., 26
Value
0x1
0xF
…
Description
0.3 pF, trimming capacitor switched on
4.5 pF, trimming capacitor switched on
CH
of these channels is defined as
AT86RF230
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