ATMEGA256RZAV-8AU Atmel, ATMEGA256RZAV-8AU Datasheet - Page 42

• Manufacturer Part Number: ATMEGA256RZAV-8AU
• Description: MCU ATMEGA2561/AT86RF230 64-TQFP
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA256RZAV-8AU

• Frequency: 2.4GHz
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: ISM, ZigBee™
• Power - Output: 3dBm
• Sensitivity: -101dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 15.5mA
• Current - Transmitting: 16.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 256kB Flash, 4kB EEPROM, 8kB RAM
• Antenna Connector: PCB, Surface Mount
• Package / Case: 64-TQFP
• Wireless Frequency: 2.4 GHz
• Interface Type: JTAG, SPI
• Output Power: 3 dBm
• For Use With: ATAVRISP2 - PROGRAMMER AVR IN SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Data Rate - Maximum: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: ATmega256

7.2.7 Register Description – Address Registers
42
AT86RF230
Bit
0x20
Read/Write
Reset value
Bit
0x21
Read/Write
Reset value
Bit
0x22
Read/Write
Reset value
Bit
0x23
Read/Write
Reset value
acknowledgment frame is set in response to a MAC command data request frame,
otherwise not. The register bit has to be set before finishing the SHR transmission of
the acknowledgment frame. This is 352 µs (192 µs ACK wait time + 160 µs SHR
transmission) after the TRX_END interrupt issued by the frame to be acknowledged.
• Bit 4 – Reserved
• Bit 3 – I_AM_COORD
This register bit has to be set if the node is a PAN coordinator. This register bit is used
for address filtering in RX_AACK. If I_AM_COORD = 1 and if only source addressing
fields are included in a data or MAC command frame, the frame shall be accepted only
if the device is the PAN coordinator and the source PAN identifier matches macPANId,
for details refer to IEEE 802.15.4-2003, section 7.5.6.2 (third-level filter rules).
• Bit [2:0] – CSMA_SEED_1
The register bits CSMA_SEED_1 contain the upper 3 bits of the CSMA_SEED. The
lower part is defined in register 0x2D (CSMA_SEED_0).
Register 0x20 (SHORT_ADDR_0)
This register contains bits [7:0] of the 16 bit short address for address filtering.
Register 0x21 (SHORT_ADDR_1)
This register contains bits [15:8] of the 16 bit short address for address filtering.
Register 0x22 (PAN_ID_0)
This register contains bits [7:0] of the 16 bit PAN ID for address filtering.
Register 0x23 (PAN_ID_1)
This register contains bits [15:8] of the 16 bit PAN ID for address filtering.
R/W
R/W
R/W
R/W
7
0
7
0
7
0
7
0
R/W
R/W
R/W
R/W
6
0
6
0
6
0
6
0
R/W
R/W
R/W
R/W
5
0
5
0
5
0
5
0
SHORT_ADDRESS_0
SHORT_ADDRESS_1
R/W
R/W
R/W
R/W
4
0
4
0
4
0
4
0
PAN_ID_0
PAN_ID_1
R/W
R/W
R/W
R/W
3
0
3
0
3
0
3
0
R/W
R/W
R/W
R/W
2
0
2
0
2
0
2
0
R/W
R/W
R/W
R/W
1
0
1
0
1
0
1
0
R/W
R/W
R/W
R/W
5131E-MCU Wireless-02/09
0
0
0
0
0
0
0
0
SHORT_ADDR_0
SHORT_ADDR_1
PAN_ID_0
PAN_ID_1