CYRF69103-40LFXC Cypress Semiconductor Corp, CYRF69103-40LFXC Datasheet - Page 57

• Manufacturer Part Number: CYRF69103-40LFXC
• Description: IC PROC 8K FLASH 40VQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: CYRFr

Specifications of CYRF69103-40LFXC

• Package / Case: 40-VQFN Exposed Pad, 40-HVQFN, 40-SQFN, 40-DHVQFN
• Frequency: 2.4GHz
• Data Rate - Maximum: 1Mbps
• Modulation Or Protocol: ISM
• Applications: General Purpose
• Power - Output: 6dBm
• Sensitivity: -87dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 21.9mA
• Current - Transmitting: 39.9mA
• Data Interface: PCB, Surface Mount
• Memory Size: 8kB Flash, 256B SRAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Processor Series: CYRF691x
• Core: M8C
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SPI
• Maximum Clock Frequency: 2 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 4
• Operating Supply Voltage: 2.5 V, 3.3 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Program Memory Type: Flash
• Program Memory Size: 8 KB
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 1.8V
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Height: 1 mm
• Length: 5.9 mm
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 1.8 V
• Width: 5.9 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1001 - ISP 4PORT CYPRESS ENCORE II MCU
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-1933

22. Radio Function Register Summary
All registers are read and writable, except where noted. Registers may be written to or read from either individually or in sequential
groups. A single-byte read or write reads or writes from the addressed register. Incrementing burst read and write is a sequence that
begins with an address, and then reads or writes to/from each register in address order for as long as clocking continues. It is possible
to repeatedly read (poll) a single register using a nonincrementing burst read.
Document #: 001-07611 Rev *F
Address
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x26
0x27
0x28
0x29
0x32
0x35
0x39
Register Files
0x20
0x21
0x22
0x23
0x24
0x25
Notes
4. b = read/write; r = read only; w = write only; ‘-’ = not used, default value is undefined.
5. SOP_CODE_ADR default = 0x17FF9E213690C782.
6. DATA_CODE_ADR default = 0x02F9939702FA5CE3012BF1DB0132BE6F.
7. PREAMBLE_ADR default = 0x333302;The count value must be great than 4 for DDR and greater than 8 for SDR
8. Registers must be configured or accessed only when the radio is in IDLE or SLEEP mode.The PMU, GPIOs, RSSI registers can be accessed in Active Tx and Rx mode.
9. EOP_CTRL_ADR[6:4] must never have the value of “000” i.e. EOP Hint Symbol count must never be “0”
10. PFET Bit: Setting this bit to "1" disables the FET, therefore safely allowing Vbat to be connected to a separate reference from Vcc when the PMU is disabled to the radio.om Vcc when the
PMU is disabled to the radio.
CHANNEL_ADR
TX_LENGTH_ADR
TX_CTRL_ADR
TX_CFG_ADR
TX_IRQ_STATUS_ADR
RX_CTRL_ADR
RX_CFG_ADR
RX_IRQ_STATUS_ADR
RX_STATUS_ADR
RX_COUNT_ADR
RX_LENGTH_ADR
PWR_CTRL_ADR
XTAL_CTRL_ADR
IO_CFG_ADR
GPIO_CTRL_ADR
XACT_CFG_ADR
FRAMING_CFG_ADR
DATA32_THOLD_ADR
DATA64_THOLD_ADR
RSSI_ADR
EOP_CTRL_ADR
CRC_SEED_LSB_ADR
CRC_SEED_MSB_ADR
TX_CRC_LSB_ADR
TX_CRC_MSB_ADR
RX_CRC_LSB_ADR
RX_CRC_MSB_ADR
TX_OFFSET_LSB_ADR
TX_OFFSET_MSB_ADR
MODE_OVERRIDE_ADR
RX_OVERRIDE_ADR
TX_OVERRIDE_ADR
XTAL_CFG_ADR
CLK_OVERRIDE_ADR
CLK_EN_ADR
RX_ABORT_ADR
AUTO_CAL_TIME_ADR
AUTO_CAL_OFFSET_ADR
ANALOG_CTRL_ADR
TX_BUFFER_ADR
RX_BUFFER_ADR
SOP_CODE_ADR
DATA_CODE_ADR
PREAMBLE_ADR
MFG_ID_ADR
Mnemonic
[9.]
XOUT OP
Not Used
Not Used
Not Used
Not Used
Not Used
AGC EN
RX ACK
PMU EN
ACK EN
SOP EN
ACK RX
IRQ OD
ACK TX
TX GO
RX GO
RXOW
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
SOP
HEN
IRQ
IRQ
OS
b7
XOUT FN
RXTX DLY
LVIRQ EN
PKT ERR
MISO OP
SOP LEN
FRC PRE
Not Used
SOPDET
Not Used
Not Used
Not Used
Not Used
Not Used
IRQ POL
TX CLR
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
LNA
IRQ
IRQ
b6
LV
MAN RXACK
DATA CODE
ABORT EN
PMU Mode
PACTL OP
XSIRQ EN
EOP ERR
FRC END
FRC SEN
MISO OD
Not Used
Not Used
Not Used
LENGTH
LEN EN
HINT
IRQEN
RXB16
IRQEN
RXB16
TXB15
TXB15
RSVD
RSVD
RSVD
RSVD
RSVD
Force
ATT
LNA
IRQ
IRQ
b5
XOUT OD
Not Used
Not Used
Not Used
IRQ OP
TXACK
IRQEN
IRQEN
disable
AUTO_CAL_OFFSET
RXDR
RSVD
RXB8
RXB8
CRC0
RSVD
RSVD
RSVD
RSVD
TXB8
TXB8
PFET
HILO
MAN
FRC
IRQ
IRQ
[10.]
AUTO_CAL_TIME
b4
CRC SEED MSB
CRC SEED LSB
SOP Code File
Data Code File
DATA MODE
FRC AWAKE
RX Buffer File
Preamble File
TX Buffer File
STRIM LSB
MFG ID File
RX Length
TX Length
CRC MSB
CRC MSB
RX Count
CRC LSB
CRC LSB
FAST TURN
OVRD ACK
START DLY
PACTL OD PACTL GPIO
END STATE
DIS CRC0
Bad CRC
Not Used
XOUT IP
IRQEN
IRQEN
RSVD
RSVD
RSVD
RSVD
TXB0
TXB0
RXB1
RXB1
Channel
IRQ
IRQ
EN
b3
LVI TH
DIS RXCRC
DIS TXCRC
TXBERR
TXBERR
RXBERR
Not Used
RXBERR
Not Used
RX Code
MISO IP
IRQEN
IRQEN
RSVD
RSVD
RSVD
RSVD
RSVD
IRQ
IRQ
SOP TH
b2
TH64
RSSI
STRIM MSB
TH32
EOP
PA SETTING
RXOW EN
PACTL IP
SPI 3PIN
Not Used
RX INV
IRQEN
IRQEN
RSVD
RSVD
RSVD
RXC
RXC
FREQ
TXC
TXC
ACE
RXF
RXF
IRQ
IRQ
b1
RX Data Mode
PMU OUTV
ACK TO
ALL SLOW
IRQ GPIO
Not Used
VLD EN
IRQEN
IRQEN
TX INV
IRQ IP
RSVD
RSVD
RSVD
RSVD
RXE
RXE
RST
TXE
TXE
IRQ
IRQ
b0
00000000
00000000
00000000
Default
00000000
00000011
00000111
00000000
00000000
10100000
00000000
1-000000
10100101
10100100
00000000
00000000
00000000
00000000
00000000
00000011
00000000
00000000
-1001000
10010-10
0-100000
0000000-
--000101
000--100
11111111
11111111
00000--0
---01010
0000----
----0100
----0000
Note [5]
Note [6]
Note [7]
--------
--------
--------
--------
--------
--------
--------
CYRF69103
NA
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Page 57 of 68
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