SX1231IMLTRT Semtech, SX1231IMLTRT Datasheet - Page 45

• Manufacturer Part Number: SX1231IMLTRT
• Description: IC 433/868/915MHZ TXRX 24-QFN
• Manufacturer: Semtech

Specifications of SX1231IMLTRT

• Frequency: 433MHz, 868MHz, 915MHz
• Data Rate - Maximum: 300kbps
• Modulation Or Protocol: FSK, GFSK, GMSK, MSK, OOK
• Applications: AMR, Home Automation, Security
• Power - Output: 13dBm
• Sensitivity: -118dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 16mA
• Current - Transmitting: 95mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 24-QFN
• Transmitting Current: 95mA
• Data Rate: 300Kbps
• Rf Ic Case Style: QFN
• No. Of Pins: 24
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Receiving Current: 16mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Lead Free Status / Rohs Status: Compliant
• Other names: SX1231IMLTR

During the comparison of the demodulated data, the first bit received is compared with bit 7 (MSB) of RegSyncValue1 and
the last bit received is compared with bit 0 (LSB) of the last byte whose address is determined by the length of the Sync
word.
When the programmed Sync word is detected the user can assume that this incoming packet is for the node and can be
processed accordingly.
SyncAddressMatch is cleared when leaving Rx or FIFO is emptied.
5.2.3.2. Configuration
Note
5.2.4. Packet Handler
The packet handler is the block used in Packet mode. Its functionality is fully described in section 5.5.
5.2.5. Control
The control block configures and controls the full chip's behavior according to the settings programmed in the configuration
registers.
5.3. Digital IO Pins Mapping
Six general purpose IO pins are available on the SX1231, and their configuration in Continuous or Packet mode is
controlled through RegDioMapping1 and RegDioMapping2.
Rev 3 - April 2010
ADVANCED COMMUNICATIONS & SENSING
Size: Sync word size can be set from 1 to 8 bytes (i.e. 8 to 64 bits) via SyncSize in RegSyncConfig. In Packet mode this
field is also used for Sync word generation in Tx mode.
Error tolerance: The number of errors tolerated in the Sync word recognition can be set from 0 to 7 bits to via SyncTol.
Value: The Sync word value is configured in SyncValue(63:0). In Packet mode this field is also used for Sync word
generation in Tx mode.
SyncAddressMatch
DCLK
Rx DATA
(NRZ)
SyncValue choices containing 0x00 bytes are not allowed
Sync_value[x]
Bit N-x =
Figure 26. Sync Word Recognition
Sync_value[1]
Bit N-1 =
Page 45
Sync_value[0]
Bit N =
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