20-101-1221 Rabbit Semiconductor, 20-101-1221 Datasheet - Page 99

• Manufacturer Part Number: 20-101-1221
• Description: RCM4400W (JAPAN TELEC CERTIFIED)
• Manufacturer: Rabbit Semiconductor
• Series: RabbitCore®r

Specifications of 20-101-1221

• Frequency: 2.4GHz
• Modulation Or Protocol: 802.11 b
• Power - Output: 16dBm
• Voltage - Supply: 3.3V
• Current - Receiving: 450mA
• Current - Transmitting: 450mA
• Data Interface: Connector, 2 x 25 Header
• Memory Size: 512K Flash, 1MB SRAM
• Antenna Connector: SMA
• Operating Temperature: -20°C ~ 85°C
• Package / Case: Module
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Applications: -
• Sensitivity: -
• Data Rate - Maximum: -
• Other names: 316-1147

Table A-6 lists the delays in gross memory access time for several values of VDD
The measurements are taken at the 50% points under the following conditions.
• T = -20°C to 85°C, V = VDD
• Internal clock to nonloaded CLK pin delay ≤ 1 ns @ 85°C/3.0 V
The clock to address output delays are similar, and apply to the following delays.
• T
• T
• T
• T
• T
• T
The data setup time delays are similar for both T
When the spectrum spreader is enabled with the clock doubler, every other clock cycle is
shortened (sometimes lengthened) by a maximum amount given in the table above. The
shortening takes place by shortening the high part of the clock. If the doubler is not
enabled, then every clock is shortened during the low part of the clock period. The maxi-
mum shortening for a pair of clocks combined is shown in the table.
Rabbit’s Technical Note TN227, Interfacing External I/O with Rabbit Microprocessor
Designs
ing I/O devices to the Rabbit 4000 microprocessors.
OEM User’s Manual
VDD
(V)
3.3
1.8
adr
CSx
IOCSx
IORD
IOWR
BUFEN
, the clock to address delay
IO
, the clock to memory chip select delay
, which is included with the online documentation
, the clock to I/O read strobe delay
, the clock to I/O write strobe delay
, the clock to I/O chip select delay
, the clock to I/O buffer enable delay
30 pF 60 pF 90 pF
Clock to Address
18
6
Output Delay
Table A-6. Preliminary Data and Clock Delays
(ns)
24
8
11
33
IO
Data Setup
Time Delay
±10%
(ns)
1
3
0.5 ns setting
setup
no dbl / dbl
2.3 / 2.3
7 / 6.5
and T
, contains suggestions for interfac-
Spectrum Spreader Delay
hold
.
Worst-Case
1 ns setting
no dbl / dbl
3 / 4.5
8 / 12
(ns)
2 ns setting
no dbl / dbl
11 / 22
4.5 / 9
IO
.
93