EM250-RTR Ember, EM250-RTR Datasheet - Page 70

• Manufacturer Part Number: EM250-RTR
• Description: IC ZIGBEE SYSTEM-ON-CHIP 48-QFN
• Manufacturer: Ember
• Series: EM250r

Specifications of EM250-RTR

• Frequency: 2.4GHz
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: Home/Building Automation, Industrial Control and Monitoring
• Power - Output: 3dBm
• Sensitivity: -97dBm
• Voltage - Supply: 2 V ~ 3.6 V
• Current - Receiving: 35.5mA
• Current - Transmitting: 33mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 5kB SRAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN
• For Use With: 636-1009 - PROGRAMMER USB FLASH EM250/260
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Rate - Maximum: -
• Other names: 636-1000-2

EM250
SC2_SPICFG [0x442C]
SC2_SPISTAT [0x4420]
70
SC_SPIRXDRV
SC_SPIMST
SC_SPIRPT
SC_SPIORD
SC_SPIPHA
SC_SPIPOL
SC_SPITXIDLE
SC_SPITXFREE
SC_SPIRXVAL
SC_SPIRXOVF
0-R
0-R
0-R
0-R
15
15
0
0
0
0
7
7
120-0082-000I
0-R
0-R
0-R
0-R
14
14
0
0
6
0
0
6
[5]
[4]
[3]
[2]
[1]
[0]
[3]
[2]
[1]
[0]
SC_SPIRXDRV
Receiver-driven mode selection bit (SPI master mode only). Clearing this bit will initiate
transactions when transmit data is available. Setting this bit will initiate transactions when
the receive buffer (FIFO or DMA) has space.
Setting this bit will put the SPI in master mode while clearing this bit will put the SPI in slave
mode.
This bit controls behavior on a transmit buffer underrun condition in slave mode. Clearing
this bit will send the BUSY token (0xFF) and setting this bit will repeat the last byte. Chang-
ing this bit will only take effect when the transmit FIFO is empty and the transmit serializer is
idle.
Clearing this bit will result in the Most Significant Bit being transmitted first while setting this
bit will result in the Least Significant Bit being transmitted first.
Clock phase configuration is selected with clearing this bit for sampling on the leading (first
edge) and setting this bit for sampling on second edge.
Clock polarity configuration is selected with clearing this bit for a rising leading edge and
setting this bit for a falling leading edge.
This bit is set when the transmit FIFO is empty and the transmitter is idle.
This bit is set when the transmit FIFO is ready to accept at least one byte.
This bit is set when the receive FIFO contains at least one byte.
This bit is set when the receive FIFO has been overrun. This bit clears when the data register
(
0-RW
SC2_DATA
0-R
0-R
0-R
13
13
0
5
0
0
5
) is read.
SC_SPIMST
0-RW
0-R
0-R
0-R
12
12
0
4
0
0
4
SC_SPITXIDLE
SC_SPIRPT
0-RW
0-R
0-R
0-R
11
11
0
3
0
3
SC_SPITXFREE
SC_SPIORD
0-RW
0-R
0-R
0-R
10
10
0
2
0
2
SC_SPIRXVAL
SC_SPIPHA
0-RW
0-R
0-R
0-R
9
0
1
9
0
1
SC_SPIRXOVF
SC_SPIPOL
0-RW
0-R
0-R
0-R
0
0
8
0
8
0