EM250-RTR Ember, EM250-RTR Datasheet - Page 101

• Manufacturer Part Number: EM250-RTR
• Description: IC ZIGBEE SYSTEM-ON-CHIP 48-QFN
• Manufacturer: Ember
• Series: EM250r

Specifications of EM250-RTR

• Frequency: 2.4GHz
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: Home/Building Automation, Industrial Control and Monitoring
• Power - Output: 3dBm
• Sensitivity: -97dBm
• Voltage - Supply: 2 V ~ 3.6 V
• Current - Receiving: 35.5mA
• Current - Transmitting: 33mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 5kB SRAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN
• For Use With: 636-1009 - PROGRAMMER USB FLASH EM250/260
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Rate - Maximum: -
• Other names: 636-1000-2

INT_EN [0x4618]
INT_EN
0-R
0-R
15
0
0
7
If another enabled interrupt of the same type occurs before being acknowledged by the software ISR, it will
be lost because no counting or queuing is used. However, this condition is detected and stored in the top-level
INT_MISS
edged” in the same way as the
If another enabled interrupt occurs after being acknowledged but while interrupts remain disabled, the CPU
will be re-interrupted to service it when the software ISR returns and interrupts are re-enabled.
Applications only have write access to certain bits in the top-level
ters that pertain to application peripherals. They have full access to second-level
INT_periphCFG
from application interference.
Applications can also trigger a software interrupt by writing into the
responsible for processing and acknowledging this interrupt.
The EM250 also provides a global
can be used to easily protect brief critical sections in application or system software.
5.6.1
0-R
0-R
14
0
0
6
[0]
Registers
register to facilitate software detection of such problems. The
IRQ enable to CPU.
registers for application peripherals. System peripheral events and masking are protected
0-R
0-R
13
0
0
5
INT_FLAG
INT_EN
0-R
0-R
12
0
0
4
enable bit to enable or disable all interrupts into the CPU. This bit
register—by writing a 1 into the corresponding bit to be cleared.
0-R
0-R
11
0
0
3
INT_FLAG
0-R
0-R
10
0
0
2
INT_SWCTRL
INT_MISS
,
INT_CFG
INT_periphFLAG
register. System software is
0-R
0-R
register is “acknowl-
0
0
9
1
, and
120-0082-000I
INT_MISS
EM250
INT_EN
and
0-RW
0-R
0
8
0
regis-
101