SI4313-B1-FM Silicon Laboratories Inc, SI4313-B1-FM Datasheet - Page 24

• Manufacturer Part Number: SI4313-B1-FM
• Description: IC RX FSK 315-915MHZ 20VQFN
• Manufacturer: Silicon Laboratories Inc
• Series: EZRadio®r
• Type: ISM Receiverr

Specifications of SI4313-B1-FM

• Package / Case: 20-VQFN
• Mfg Application Notes: Si4313 Register Desc AppNote
• Frequency: 315MHz, 434MHz, 868MHz, 915MHz
• Sensitivity: -118dBm
• Data Rate - Maximum: 128kbps
• Modulation Or Protocol: FSK, GFSK, OOK
• Applications: Data Logging, Health Monitors, Remote Control, Weather Station
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Voltage - Supply: 1.8 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Operating Frequency: 315 MHz to 915 MHz
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Current: 100 nA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Memory Size: -
• Current - Receiving: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1980-5

Si4313-B1
(AFCLimiter) which is located in register 2Ah.
The AFC Limiter register is an unsigned register and its value can be obtained from the EZRadioPRO Register
Calculator spreadsheet or from WDS.
The amount of error correction feedback to the Fractional-N PLL before the preamble is detected is controlled from
afcgearh[2:0]. The default value 000 relates to a feedback of 100% from the measured frequency error and is
advised for most applications. Every bit added will half the feedback but will require a longer preamble to settle.
The AFC operates as follows. The frequency error of the incoming signal is measured over a period of two bit
times, after which it corrects the local oscillator via the Fractional-N PLL. After this correction, some time is allowed
to settle the Fractional-N PLL to the new frequency before the next frequency error is measured. The duration of
the AFC cycle before the preamble is detected can be programmed with shwait[2:0]. It is advised to use the default
value 001, which sets the AFC cycle to 4 bit times (2 for measurement and 2 for settling).
The AFC correction value may be read from register 2Bh. The value read can be converted to kHz with the
following formula:
24
AFC disabled
AFC enabled
AFC_pull_in_range = ±AFCLimiter[7:0] x (hbsel+1) x 625 Hz
AFC Correction = 156.25Hz x (hbsel +1) x afc_corr[7: 0]
Freq Offset Register
AFC
RX
Rev. 1.0
Frequency Correction
Freq Offset Register
Freq Offset Register
TX