SX1210I084T Semtech, SX1210I084T Datasheet - Page 3

• Manufacturer Part Number: SX1210I084T
• Description: IC SINGLE-CHIP RECEIVER 32-TQFN
• Manufacturer: Semtech

Specifications of SX1210I084T

• Frequency: 863MHz ~ 960MHz
• Sensitivity: -113dBm
• Data Rate - Maximum: 200 kbps
• Modulation Or Protocol: FSK, OOK
• Applications: Alarm Systems, Communication Systems
• Current - Receiving: 3mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Voltage - Supply: 2.1 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-TQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Memory Size: -

Index of Figures
Figure 1: SX1210 Simplified Block Diagram .................................. 5
Figure 2: SX1210 Pin Diagram ...................................................... 6
Figure 3: SX1210 Detailed Block Diagram .................................. 12
Figure 4: Power Supply Breakdown............................................. 13
Figure 5: Frequency Synthesizer Description .............................. 14
Figure 6: LO Generator ................................................................ 14
Figure 7: Loop Filter ..................................................................... 16
Figure 8: Receiver Architecture ................................................... 17
Figure 9: FSK Receiver Setting ................................................... 17
Figure 10: OOK Receiver Setting ................................................ 17
Figure 11: Active Channel Filter Description................................ 18
Figure 12: Butterworth Filter's Actual BW .................................... 20
Figure 13: Polyphase Filter's Actual BW...................................... 20
Figure 14: RSSI Dynamic Range ................................................. 21
Figure 15: RSSI IRQ Timings ...................................................... 22
Figure 16: OOK Demodulator Description ................................... 23
Figure 17: Floor Threshold Optimization...................................... 24
Figure 18: BitSync Description..................................................... 25
Figure 19: SX1210’s Data Processing Conceptual View ............. 28
Figure 20: SPI Interface Overview and uC Connections ............. 29
Figure 21: Write Register Sequence ............................................ 30
Figure 22: Read Register Sequence............................................ 31
Figure 23: Read Bytes Sequence (ex: 2 bytes) ........................... 31
Figure 24: FIFO and Shift Register (SR)...................................... 32
Figure 25: FIFO Threshold IRQ Source Behavior........................ 33
Figure 26: Sync Word Recognition .............................................. 33
Figure 27: Continuous Mode Conceptual View............................ 35
Figure 28: Rx Processing in Continuous Mode............................ 36
Figure 29: uC Connections in Continuous Mode ......................... 37
Figure 30: Buffered Mode Conceptual View ................................ 38
Rev 2– Sept 8
ADVANCED COMMUNICATIONS & SENSING
th
, 2008
Page 3 of 73
Figure 31: Rx Processing in Buffered Mode (FIFO size=16,
Fifo_fill_method=0) .......................................................................39
Figure 32: uC Connections in Buffered Mode...............................40
Figure 33: Packet Mode Conceptual View....................................41
Figure 34: Fixed Length Packet Format........................................42
Figure 35: Variable Length Packet Format ...................................43
Figure 36: CRC Implementation ...................................................45
Figure 37: Manchester Decoding..................................................45
Figure 38: Data Whitening Implementation...................................46
Figure 39: uC Connections in Packet Mode .................................46
Figure 40: Optimized Rx Cycle .....................................................58
Figure 41: Rx Hop Cycle...............................................................59
Figure 42: POR Timing Diagram...................................................60
Figure 43: Manual Reset Timing Diagram ....................................60
Figure 44: Reference Design Circuit Schematic ...........................61
Figure 45: Reference Design‘s Stackup .......................................62
Figure 46: Reference Design Layout (top view)............................62
Figure 49: Sensitivity Across the 868 MHz Band..........................65
Figure 50: Sensitivity Across the 915 MHz Band..........................65
Figure 51: FSK Sensitivity Loss vs. LO Drift .................................66
Figure 52: OOK Sensitivity Loss vs. LO Drift ................................66
Figure 53: FSK Sensitivity vs. Rx BW...........................................67
Figure 54: OOK Sensitivity Change vs. Rx BW ............................67
Figure 55: Sensitivity Stability .......................................................68
Figure 56: FSK Sensitivity vs. BR .................................................68
Figure 57: OOK Sensitivity vs. BR ................................................69
Figure 58: ACR in FSK Mode .......................................................69
Figure 59: ACR in OOK Mode ......................................................70
Figure 60: Package Outline Drawing ............................................71
Figure 61: PCB Land Pattern........................................................71
Figure 62: Tape & Reel Dimensions .............................................72
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