SX1210I084T Semtech, SX1210I084T Datasheet - Page 16

• Manufacturer Part Number: SX1210I084T
• Description: IC SINGLE-CHIP RECEIVER 32-TQFN
• Manufacturer: Semtech

Specifications of SX1210I084T

• Frequency: 863MHz ~ 960MHz
• Sensitivity: -113dBm
• Data Rate - Maximum: 200 kbps
• Modulation Or Protocol: FSK, OOK
• Applications: Alarm Systems, Communication Systems
• Current - Receiving: 3mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Voltage - Supply: 2.1 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-TQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Memory Size: -

Following the recommendations made in section 3.2.4, the loop filter proposed in the reference design’s bill of
material on section 7.5.3 should be used. The loop filter settings are frequency band independent and are hence
relevant to all implementations of the SX1210.
The SX1210 also features a PLL lock detect indicator. This is useful for optimizing power consumption, by adjusting
the synthesizer wake up time (TS_FS), since the PLL startup time is lower than specified under nominal conditions.
The lock status can be read on bit IRQParam_PLL_lock, and must be cleared by writing a “1” to this same register.
In addition, the lock status can be reflected in pin 23 PLL_LOCK, by setting the bit IRQParam_Enable_lock_detect.
As shown in Figure 5 the PLL structure comprises three different dividers, R, P and S, which set the output
frequency through the LO. A second set of dividers is also available to allow rapid switching between a pair of
frequencies: R1/P1/S1 and R2/P2/S2. These six dividers are programmed by six bytes of the register MCParam
from addresses 6 to 11.
The following formula gives the relationship between the local oscillator, and R, P and S values, when using FSK
modulation.
Due to the low intermediate frequency (Low-IF) architecture of the SX1210 the frequency should be configured so
as to ensure the correct low-IF receiver baseband center frequency, IF2.
Note that from Section 3.3.4, it is recommended that IF2 be set to 100 kHz.
Rev 2– Sept 8
ADVANCED COMMUNICATIO
3.2.7. PLL Lock Detection Indicator
3.2.8. Frequency Calculation
th
, 2008
3.2.8.1. FSK Mode
3.2.8.2. OOK Mode
NS & SENSING
Frf
Frf
CL2
Frf
Frf
,
,
ook
ook
,
,
fsk
fsk
=
=
Figure 7: Loop Filter
9
8
9
8
=
=
RL1
Flo
Fxtal
R
9
8
9
8
CL1
Page 16 of 73
+
Flo
Fxtal
R
−
1
+
IF
[
75
1
2
[
(
75
P
(
+
P
) 1
LF_M
LF_P
+
+
) 1
S
+
)
]
S
−
)
IF
]
2
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SX1210