AD6624AABC Analog Devices Inc, AD6624AABC Datasheet - Page 36

• Manufacturer Part Number: AD6624AABC
• Description: IC RCVR SGNL PROC QUAD 196CSPBGA
• Manufacturer: Analog Devices Inc
• Series: AD6624r

Specifications of AD6624AABC

• Rohs Status: RoHS non-compliant
• Rf Type: Cellular, CDMA2000, EDGE, GPRS, GSM
• Number Of Mixers: 1
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 196-CSPBGA
• Current - Supply: -
• Frequency: -
• Gain: -
• Noise Figure: -
• Secondary Attributes: -

AD6624A
Input Port Control Registers
The Input Port control register enables various input-related
features used primarily for input detection and level control.
Depending on the mode of operation, up to four different signal
paths can be monitored with these registers. These features are
accessed by setting Bit 5 of external address 3 (Sleep Register)
and then using the CAR (external address 6) to address the
eight available locations.
Response to these settings is directed to the LIA-A, LIA-B, LIB-A
and LIB-B pins.
Address 00 is the lower threshold for Input Channel A. This
word is 10 bits wide and maps to the 10 most significant bits
of the mantissa. If the upper 10 bits are less than or equal to this
value, the lower threshold has been met. In normal chip operation,
this starts the dwell time counter. If the input signal increases
above this value, the counter is reloaded and awaits the input to
drop back to this level.
Address 01 is the upper threshold for Input Channel A. This
word is 10 bits wide and maps to the 10 most significant bits of
the mantissa. If the upper 10 bits are greater than or equal to
this value, the upper threshold has been met. In normal chip
operation, this will cause the appropriate LI pin (LIA–A or
LIA–B) to become active.
Address 02 is the dwell time for input Channel A. This sets the
time that the input signal must be at or below the lower threshold
before the LI pin is deactivated. For the input level detector to
work, the dwell time must be set to at least one. If set to zero,
the LI functions are disabled.
Address 02 has a 20-bit register. When the lower threshold is
met following an excursion into the upper threshold, the dwell
time counter is loaded and begins to count high-speed clock
cycles as long as the input is at or below the lower threshold.
If the signal increases above the lower threshold, the counter
is reloaded and waits for the signal to fall below the lower
threshold again.
Address 03 configures Input Channel A.
Bit 4 determines the polarity of LIA-A and LIA-B. If this bit is
cleared, the LI signal is high when the upper threshold has been
exceeded. However, if this bit is set, the LI pin is low when active.
This allows maximum flexibility when using this function.
Bit 3 determines if the input consists of a single channel or
TDM channels such as when using the AD6600. If this bit is
cleared, a single ADC is assumed. In this mode, LIA–A functions
as the active output indicator. LIA–B provides the complement of
LIA–A. However, if this bit is set, the input is determined to be
dual channel and determined by the state of the IENA pin. If
SCLK
SDI
FRAME
X
X
X
A2
t
SSI
A1
FRAME
A0
D7
t
HSI
the IENA pin is low, the input detection is directed to LIA–A.
If the IENA pin is high, the input is directed to LIA–B. In
either case, Bit 4 determines the actual polarity of these signals.
Bits 2–0 determine the internal latency of the gain detect func-
tion. When the LIA–A, B pins are made active, they are typically
used to change an attenuator or gain stage. Since this is prior to
the ADC, there is a latency associated with the ADC and with the
settling of the gain change. This register allows the internal delay
of the LIA–A, B signal to be programmed.
Addresses 4–7 duplicate address 00–03 for Input Port B
(INB[13:0]).
SERIAL PORT CONTROL
The AD6624A will have four serial ports serving as primary data
output interfaces. In addition to output data, these ports will
provide control paths to the internal functions of the AD6624A.
Serial Port 0 (SDIN0) can access all of the internal registers for
all of the channels while Ports 1, 2, and 3 (SDIN1–3) are limited
to their local registers only. In this manner, a single DSP could
be used to control the AD6624A over the Serial Port 0 inter-
face. The option is present to use a DSP per channel if needed.
In addition to the global access of Serial Port 0, it has preemp-
tive access over the other serial ports and the microport.
The Serial Output and Input functions use mainly separate
hardware and can largely be considered separate ports that
use a common Serial Clock (SCLK). The Serial Input Port is self-
framing as described below and allows more efficient use of the
Serial Input Bandwidth for Programming. Hence, the state of
the SDFS signal has no direct impact on the Serial Input Port.
Since the Serial Input Port is self-framing, it is not necessary to
wait for an SDFS to perform a serial write. The beginning of a
Serial Input Frame is signaled by a FRAME bit that appears on
the SDI pin. This is the MSB of the Serial Input Frame. After
the FRAME bit has been sampled high on the falling edge of
SCLK a State Counter will start and enable an 11-bit Serial
Shifter four serial clock cycles later. These four SCLK cycles
represent the “don’t care” bits of the Serial Frame that are
ignored. After all of the bits are shifted, the Serial Input Port will
pass along the 8-bit data and 3-bit address to the arbitration block.
The Serial Word Structure for the SDI input is illustrated in the
table below. Only 15 bits are listed so that the second bit in a
standard 16-bit serial word is considered the FRAME bit. This
is done for compatibility with the AD6620 Serial Input Port.
The shifting order begins with FRAME and shifts the address
MSB first and then the data MSB first.
CLKn
D6
D5
D4
D3
X
D2
D1
D0