AD6624AABC Analog Devices Inc, AD6624AABC Datasheet
AD6624AABC
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AD6624AABC Summary of contents
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PRODUCT DESCRIPTION The AD6624A is a four-channel (quad) digital receive signal processor (RSP) with four cascaded signal-processing elements: a frequency translator, two fixed-coefficient decimating filters, and a programmable-coefficient decimating filter. INA[13: EXPA[2:0] IENA LIA-A LIA ...
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AD6624A TABLE OF CONTENTS FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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SPECIFICATIONS (VDD = 2.5 V RECOMMENDED OPERATING CONDITIONS Test Parameter Level Min VDD IV 2.375 VDDIO IV 3 –40 AMBIENT ELECTRICAL CHARACTERISTICS Parameter (Conditions) LOGIC INPUTS (5 V TOLERANT) Logic Compatibility Logic “1” Voltage Logic “0” Voltage Logic ...
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AD6624A GENERAL TIMING CHARACTERISTICS Parameter (Conditions) CLK Timing Requirements: t CLK Period CLK t CLK Width Low CLKL t CLK Width High CLKH RESET Timing Requirement: RESET Width Low t RESL Input Wideband Data Timing Requirements: Input to ↑CLK Setup ...
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MICROPROCESSOR PORT TIMING CHARACTERISTICS Parameter (Conditions) MICROPROCESSOR PORT, MODE INM (MODE = 0) MODE INM Write Timing: to ↑CLK Setup Time 3 t Control SC to ↑CLK Hold Time 3 t Control HC WR(RW) to RDY(DTACK) Hold Time t HWR ...
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AD6624A TIMING DIAGRAMS t CLK t CLKL CLK t CLKH t DLI LIA-A LIA-B LIB-A LIB-B RESET t SSF RESET CLK IN[13:0] DATA EXP[2:0] SCLK t DSDFS SDFS t SSI SDI SDFE CLK t DSCLKH SCLK ...
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DSDO SCLK I I SDO 15 14 SDFE CLK t DDR DR SCLK t DSDR DR t DSDFE SCLK SDFS CLK IN[13:0] EXP[2:0] IEN CLK SYNCA SYNCB SYNCC SYNCD AD6624A t t SSF HSF t ...
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AD6624A TIMING DIAGRAMS—INM MICROPORT MODE CLK RD(DS HWR SC WR(RW HAM SAM A[2:0] VALID ADDRESS t t HAM SAM D[7:0] VALID DATA t DRDY RDY (DTACK) t ACC NOTES 1. t ACCESS TIME ...
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... JA Thermal measurements made in the horizontal position on a 4-layer board. Model Temperature Range AD6624AABC –40°C to +85°C (Ambient) AD6624AS/PCB CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. ...
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AD6624A 1.0mm INB5 INB6 B INB3 INB4 C INB1 INB8 D LIB-B INB2 INB0 E CLK ...
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PIN FUNCTION DESCRIPTIONS 196-LEAD BGA Pin No. Type POWER SUPPLY VDD P VDDIO P GND G INPUTS 1 INA[13: EXPA[2: IENA I 1 INB[13: EXPB[2: IENB I RESET I CLK I 1 ...
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AD6624A PIN FUNCTION DESCRIPTIONS 196-LEAD BGA (continued) Pin No. Type OUTPUT LIA-A O LIA-B O LIB-B O LIB SDO0 O/T 1 SDO1 O/T 1 SDO2 O/T 1 SDO3 O/T DR0 O DR1 O DR2 O DR3 O JTAG ...
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ARCHITECTURE The AD6624A has four signal processing stages: a Frequency Translator, second order Resampling Cascaded Integrator Comb FIR filters (rCIC2), a fifth order Cascaded Integrator Comb FIR filter (CIC5) and a RAM Coefficient FIR filter (RCF). Multiple modes are supported ...
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AD6624A EXAMPLE FILTER RESPONSE The filter in Figure 19 is based MSPS input data rate and an output rate of 541.6666 kSPS (two samples per symbol for EDGE). Total decimation rate is 120 distributed between the rCIC2, ...
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A typical application for this feature would be to take the data from an AD6600 Diversity ADC to one of the inputs of the AD6624A. The A/B_OUT from that chip would be tied to the IEN. One channel within the ...
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AD6624A Input Data Scaling The AD6624A has two data input ports Input Port and a B Input Port. Each accepts 14-bit mantissa (two’s-complement integer) IN[13:0], a 3-bit exponent (unsigned integer) EXP[2:0] and the Input Enable (IEN). Both inputs ...
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It also allows the AD6624A to be tailored in a system that employs the AD6600, but does not utilize all of its signal range. For example, if only the first four RSSI ranges are expected to occur, the ExpOff could ...
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AD6624A lowered, input data is replaced with zero values. During this period, the NCO continues to run such that when the IEN line is raised again, the NCO value will be at the value it would have otherwise been in ...
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S ceil log M floor rCIC 2 2 rCIC 2 × rCIC 2 OL input level _ CIC 2 × ...
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AD6624A Bit 11 of this register is used to invert the external exponent before internal calculation. This bit should be set HIGH for gain-ranging ADCs that use an increasing exponent to represent an increasing signal level. This bit should be ...
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I IN 160 20b I-RAM 256 20b C-RAM Q IN 160 20b Q-RAM RCF Decimation Register Each RCF channel can be used to decimate the data rate. The decimation register is an 8-bit register and can decimate from 1 to ...
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AD6624A Bit 8 is the RCF bank select bit used to program the register. When this bit is 0, the lowest block of 128 is selected (Taps 0 through 127). When high, the highest block is selected (Taps 128 through ...
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MICRO SHADOW REGISTER REGISTER I31 Q31 I31 Q31 FROM MICROPORT NCO FREQUENCY UPDATE HOLD-OFF COUNTER B0 AD6624 CLK B15 SOFT SYNC ENABLE TC ENB PIN SYNC ENABLE Start Start refers to the start- individual ...
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AD6624A 1. Note that the time from when RDY (Pin 57) goes high to when the NCO begins processing data is the contents of the NCO Freq Hold-Off counter (0x84) plus seven master clock cycles. 2. Write the NCO Freq ...
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...
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AD6624A To configure a channel as a serial bus master, Bit 4 of register 0xA9 should be set high. However, as with the SDIV pins, Channel 0 SBM is not mapped to memory and is instead pinned out and must ...
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Ch Address Register 00–7F Coefficient Memory (CMEM) 80 CHANNEL SLEEP 81 Soft_Sync Control Register 82 Pin_SYNC Control Register 83 Start Hold-Off Counter 84 NCO Frequency Hold-Off Counter 85 NCO Frequency Register 0 86 NCO Frequency Register 1 87 NCO Phase ...
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AD6624A Table VIII. Channel Address Memory Map (continued) Ch Address Register A5 BIST Signature for I Path A6 BIST Signature for Q Path BIST Outputs to Accumulate A8 RAM BIST Control Register A9 Serial Port Control Register ...
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DSDFS SCLK SDFS SDFE t DSDO SCLK I I SDO 15 14 SDFE SBM0 SBM0 is the Serial Bus Master pin for the Channel 0 Serial Port only. Serial Ports 1, 2, and 3 will always default to Serial ...
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AD6624A for I and 12 more bits for Q). If set to ‘01,’ the serial words are 16 bits wide, and if set to ‘1x’ don’t care), the word length is 24 bits. SDFS Mode Bits 8–7 of ...
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NCO Phase Offset Register This register represents a 16-bit phase offset to the NCO. It can be interpreted as values ranging from 0 to just under 2 π. 0x88: NCO Control Register This 9-bit register controls features of the ...
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AD6624A register which allows decimation up to 256, for most filtering scenarios, the decimation should be limited to values between 1 and 32. Higher decimations are allowed, but the alias protection of the RCF may not be acceptable for some ...
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Serial Port Control Register This register controls the serial port of the AD6624A and, along with the RCF control register, it helps to determine the output format. Bit 9 of this register allows the RCF or CIC5 data to ...
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AD6624A Access Control Register (ACR) The Access Control Register serves to define the channel or channels that receive an access from the microport or Serial Port 0. Bit 7 of this register is the autoincrement bit. If this bit is ...
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Table XIII. Memory Map for Input Port Control Registers Ch Address Register 00 Lower Threshold A 01 Upper Threshold A 02 Dwell Time A 03 Gain Range A Control Register 04 Lower Threshold B 05 Upper Threshold B 06 Dwell ...
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AD6624A Input Port Control Registers The Input Port control register enables various input-related features used primarily for input detection and level control. Depending on the mode of operation four different signal paths can be monitored with these registers. ...
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JTAG BOUNDARY SCAN The AD6624A supports a subset of IEEE Standard 1149.1 specifi- cations. For additional details of the standard, please see “IEEE Standard Test Access Port and Boundary-Scan Architecture,” IEEE-1149 publication from IEEE. The AD6624A has five pins associated ...
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AD6624A INTERNAL READ ACCESS A read is performed by first writing the CAR and AMR as with a write. The data registers (DR2–DR0) are then read in the reverse order that they were written. First, the least significant byte of ...
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OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 196-Lead PBGA (BC-196) 0.594 (15.10) 0.591 (15.00) SQ 0.039 (1.00) 0.587 (14.90) BALL PITCH BALL A1 INDICATOR 0.512 (13.0) TOP VIEW 0.059 (1.50) DETAIL A 0.039 (1.00) MAX 0.033 (0.85) 0.021 (0.53) ...
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