AD6624AABC Analog Devices Inc, AD6624AABC Datasheet - Page 31

• Manufacturer Part Number: AD6624AABC
• Description: IC RCVR SGNL PROC QUAD 196CSPBGA
• Manufacturer: Analog Devices Inc
• Series: AD6624r

Specifications of AD6624AABC

• Rohs Status: RoHS non-compliant
• Rf Type: Cellular, CDMA2000, EDGE, GPRS, GSM
• Number Of Mixers: 1
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 196-CSPBGA
• Current - Supply: -
• Frequency: -
• Gain: -
• Noise Figure: -
• Secondary Attributes: -

0x87: NCO Phase Offset Register
This register represents a 16-bit phase offset to the NCO. It can
be interpreted as values ranging from 0 to just under 2 π.
0x88: NCO Control Register
This 9-bit register controls features of the NCO and the channel.
The bits are defined below. For more detail, the NCO section
should be consulted.
Bits 8–7 of this register choose which of the four SYNC pins are
used by the channel. The SYNC pin selected can be used to
initiate a START, HOP, or timing adjustment to the channel.
The Synchronization section of this data sheet provides more
details on this.
Bit 6 of this register defines whether the A or B Input Port is used
by the channel. If this bit is low, the A Input Port is selected and
if this bit is high the B Input Port is selected. Each input port
consists of a 14-bit input mantissa (INx[13:0]), a 3-bit exponent
(EXPx[2:0]), and an input enable pin, IENx. The x represents
either A or B.
Bits 5–4 determine how the sample clock for the channel is
derived from the high-speed CLK signal. There are four possible
choices. Each is defined below but for further detail, the NCO
section of the data sheet should be consulted.
When these bits are 00, the input sample rate (f
channel is equal to the rate of the high-speed CLK signal. When
IEN is low, the data going into the channel is masked to 0. This
is an appropriate mode for TDD systems where the receiver
may wish to mask off the transmitted data yet still remain in the
proper phase for the next receive burst.
When these bits are 01, the input sample rate is determined by
the fraction of the rising edges of CLK on which the IEN input
is high. For example, if IEN toggles on every rising edge of
CLK, then the IEN signal will only be sampled high on one out
of every two rising edges of CLK. This means that the input
sample rate f
When these bits are 10, the input sample rate is determined by
the rate at which the IEN pin toggles. The data that is captured
on the rising edge of CLK after IEN transitions from low to
high is processed. When these bits are 11, the accumulator and
sample CLK are determined by the rate at which the IEN pin
toggles. The data that is captured on the rising edge of CLK
after IEN transitions from high to low is processed. For example,
Control Modes 10 and 11 can be used to allow interleaved data
from either the A or B Input Ports and then assigned to the respec-
tive channel. The IEN pin selects the data such that a channel
could be configured in Mode 10 and another could be configured
in Mode 11.
Bit 3 determines whether or not the phase accumulator of the
NCO is cleared when a Hop occurs. The Hop can originate
from either the Pin_SYNC or Soft_SYNC. When this bit is set
to 0, the Hop is phase continuous and the accumulator is not
cleared. When this bit is set to 1, the accumulator is cleared to 0
before it begins accumulating the new frequency word. This is
appropriate when multiple channels are hopping from different
frequencies to a common frequency.
Bits 2–1 control whether or not the dithers of the NCO are
activated. The use of these features is heavily determined by the
system constraints. Consult the NCO section of the data sheet
for more detailed information on the use of dither.
SAMP
will be 1/2 the CLK rate.
SAMP
) of the
Bit 0 of this register allows the NCO Frequency translation stage to
be bypassed. When this occurs, the data from the A Input Port
is passed down the I path of the channel and the data from the
B Input Port is passed down the Q path of the channel. This allows
a real filter to be performed on baseband I and Q data.
0x90: rCIC2 Decimation – 1 (M
This register is used to set the decimation in the rCIC2 filter. The
value written to this register is the decimation minus one. The
rCIC2 decimation can range from 1 to 4096 depending upon the
interpolation of the channel. The decimation must always be
greater than the interpolation. M
L
Scalar can be chosen. For more details, consult the rCIC2 section.
0x91: rCIC2 Interpolation – 1 (L
This register is used to set the interpolation in the rCIC2 filter.
The value written to this register is the interpolation minus one.
The rCIC2 interpolation can range from 1 to 512 depending
upon the decimation of the rCIC2. There is no timing error
associated with this interpolation. See the rCIC2 section of the
data sheet for further details.
0x92: rCIC2 Scale
The rCIC2 scale register is used to provide attenuation to compen-
sate for the gain of the rCIC2 and to adjust the linearization of
the data from the floating-point input. The use of this scale
register is influenced by both the rCIC2 growth and floating-
point input port considerations. The rCIC2 section should be
consulted for details. The rCIC2 scalar has been combined with
the Exponent Offset and will need to be handled appropriately
in both the Input Port and rCIC2 sections.
Bit 11 determines the polarity of the exponent. Normally, this
bit will be cleared unless an ADC such as the AD6600 is used,
in which case, this bit will be set.
Bit 10 determines the weight of the exponent word associated
with the input port. When this bit is low, each exponent step is
considered to be worth 6.02 dB. When this bit is high, each
exponent step is considered to be worth 12.02 dB.
Bits 9–5 are the actual scale values used when the Level Indicator,
LI pin associated with this channel is active.
Bits 4–0 are the actual scale values used when the Level Indicator,
LI pin associated with this channel is inactive.
0x93:
Reserved. (Must be written low.)
0x94: CIC5 Decimation – 1 (M
This register is used to set the decimation in the CIC5 filter.
The value written to this register is the decimation minus one.
Although this is an 8-bit register, the decimation is usually limited
to values between 1 and 32. Decimations higher than 32 would
require more scaling than the CIC5’s capability.
0x95: CIC5 Scale
The CIC5 scale factor is used to compensate for the growth of
the CIC5 filter. Consult the CIC5 section for details.
0x96:
Reserved. (Must be written low.)
0xA0: RCF Decimation – 1 (M
This register is used to set the decimation of the RCF stage. The
value written is the decimation minus one. Although this is an 8-bit
rCIC2
and both must be chosen such that a suitable rCIC2
rCIC2
RCF
CIC5
rCIC2
rCIC2
–1)
–1)
must be chosen larger than
–1)
–1)
AD6624A