AD6624AABC Analog Devices Inc, AD6624AABC Datasheet - Page 28

• Manufacturer Part Number: AD6624AABC
• Description: IC RCVR SGNL PROC QUAD 196CSPBGA
• Manufacturer: Analog Devices Inc
• Series: AD6624r

Specifications of AD6624AABC

• Rohs Status: RoHS non-compliant
• Rf Type: Cellular, CDMA2000, EDGE, GPRS, GSM
• Number Of Mixers: 1
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 196-CSPBGA
• Current - Supply: -
• Frequency: -
• Gain: -
• Noise Figure: -
• Secondary Attributes: -

AD6624A
Serial Output Frame Timing (Master and Slave)
The SDFS signal transitions accordingly depending on whether
the part is in Master (SBM = 1, Figure 43) or Slave (SBM = 0,
Figure 32) mode. The next rising edge of SCLK after this occurs
will drive the first bit of the serial data on the SDO pin. The
falling edge of SCLK or the subsequent rising edge can then be
used by the DSP to sample the data until the required number
of bits is received (determined by the serial output port word
length). If the DSP has the ability to count bits, the DSP will
know when the complete frame is received. If not, the DSP can
monitor the SDFE pin to determine that the frame is complete.
Serial Port Timing Specifications
Whether the AD6624A serial channel is operated as a Serial
Bus Master or as a Serial Slave, the serial port timing is iden-
tical. Figures 38 to 44 indicate the required timing for each of
the specifications.
SCLK
Ch Address
A5
A6
A7
A8
A9
CLK
SCLK
t
DSCLKH
Register
BIST Signature for I Path
BIST Signature for Q Path
# of BIST Outputs to Accumulate
RAM BIST Control Register
Serial Port Control Register
t
SCLKL
t
SCLKL
t
SCLKH
t
SCLK
Table VIII. Channel Address Memory Map (continued)
t
SCLKH
Bit Width
16
16
20
3
10
SCLK
SDFS
SDO
SCLK
SDO
SCLK
SCLK
SDFS
SDI
RISING SCLK AFTER SDFS GOES HIGH
FIRST DATA IS AVAILABLE THE FIRST
Comments
BIST-I
BIST-Q
19–0: # of Outputs (Counter Value Read)
2:
1:
0:
9:
8–7:
6–5:
4:
3–0:
D-RAM Fail/Pass
C-RAM Fail/Pass
RAM BIST Enable
Map RCF Data to BIST Registers
I_SDFS Control
1x:
01:
00:
SOWL
1x:
01:
00:
SBMx
SDIVx[3:0]
t
SSF
t
DSDO
t
Separate I and Q SDFS Pulses
SDFS High for Entire Frame
Single SDFS Pulse
24-Bit Words
16-Bit Words
12-Bit Words
SSI
DATA
I
15
t
DSO
t
HSI
t
HSF
I
14
I
MSB
SDFS MINIMUM
WIDTH IS ONE SCLK
I
13
I
MSB1