MCP2030-I/ST Microchip Technology, MCP2030-I/ST Datasheet - Page 54

• Manufacturer Part Number: MCP2030-I/ST
• Description: IC KEYLESS ENTRY AFE 14TSSOP
• Manufacturer: Microchip Technology

Specifications of MCP2030-I/ST

• Rf Type: ISM
• Frequency: 125kHz
• Features: 10kbps
• Package / Case: 14-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

MCP2030
REGISTER 5-6:
REGISTER 5-7:
DS21981A-page 54
bit 8
bit 7
bit 6-5
bit 4-1
bit 0
Legend:
R = Readable bit
-n = Value at POR
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Legend:
R = Readable bit
-n = Value at POR
AUTOCHSEL: Auto-Channel Select bit
1 = Enabled – Device selects channel(s) that has demodulator output “high” at the end of T
0 = Disabled – Device follows channel enable/disable bits defined in Register 0
AGCSIG: Demodulator Output Enable bit, after the AGC loop is active
1 = Enabled – No output until AGC is regulating at around 20
0 = Disabled – The device passes signal of any level it is capable of detecting
MODMIN<1:0>: Minimum Modulation Depth bit
00 = 33%
01 = 60%
10 = 14%
11 = 8%
LCZSEN<3:0>
0000 = -0 dB (Default)
1111 = -30 dB
R5PAR: Register 5 Parity bit – set/cleared so the 9-bit register contains odd parity – an odd number of set bits
bit 8
AUTOCHSEL
bit 8
COLPAR7: Set/Cleared so that this 8th parity bit + the sum of the Config. register row parity bits contain an odd
number of set bits.
COLPAR6: Set/Cleared such that this 7th parity bit + the sum of the 7th bits in Config. registers 0 through 5 contain
an odd number of set bits.
COLPAR5: Set/Cleared such that this 6th parity bit + the sum of the 6th bits in Config. registers 0 through 5 contain
an odd number of set bits.
COLPAR4: Set/Cleared such that this 5th parity bit + the sum of the 5th bits in Config. registers 0 through 5 contain
an odd number of set bits.
COLPAR3: Set/Cleared such that this 4th parity bit + the sum of the 4th bits in Config. registers 0 through 5 contain
an odd number of set bits.
COLPAR2: Set/Cleared such that this 3rd parity bit + the sum of the 3rd bits in Config. registers 0 through 5 contain
an odd number of set bits.
COLPAR1: Set/Cleared such that this 2nd parity bit + the sum of the 2nd bits in Config. registers 0 through 5 contain
an odd number of set bits.
COLPAR0: Set/Cleared such that this 1st parity bit + the sum of the 1st bits in Config. registers 0 through 5 contain
an odd number of set bits.
R6PAR: Register 6 Parity bit – set/cleared so the 9-bit register contains odd parity – an odd number of set bits
COLPAR7
Note 1: Assured monotonic increment (or decrement) by design.
R/W-0
R/W-0
CONFIGURATION REGISTER 5 (ADDRESS: 0101)
COLUMN PARITY REGISTER 6 (ADDRESS: 0110)
blocks the channel(s).
is set when the AGC begins regulating.
:
COLPAR6
(1)
R/W-0
AGCSIG
W = Writable bit
‘1’ = Bit is set
: LCZ Sensitivity Reduction bit
R/W-0
W = Writable bit
‘1’ = Bit is set
COLPAR5
MODMIN1 MODMIN0 LCZSEN3 LCZSEN2 LCZSEN1 LCZSEN0 R5PAR
R/W-0
R/W-0
COLPAR4
R/W-0
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
COLPAR3
R/W-0
R/W-0
mV
COLPAR2 COLPAR1
R/W-0
PP
R/W-0
at input pins. The AGC Active Status bit
© 2005 Microchip Technology Inc.
R/W-0
R/W-0
x = Bit is unknown
x = Bit is unknown
COLPAR0
R/W-0
AGC
R/W-0
; or otherwise,
R6PAR
R/W-0
R/W-0
bit 0
bit 0