MCP2030-I/ST Microchip Technology, MCP2030-I/ST Datasheet - Page 48

• Manufacturer Part Number: MCP2030-I/ST
• Description: IC KEYLESS ENTRY AFE 14TSSOP
• Manufacturer: Microchip Technology

Specifications of MCP2030-I/ST

• Rf Type: ISM
• Frequency: 125kHz
• Features: 10kbps
• Package / Case: 14-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

MCP2030
FIGURE 5-11:
DS21981A-page 48
LFDATA/RSSI/
MCU SPI Read Details:
1.
2.
3.
4.
5.
6.
SCLK/ALERT
Note:
CCLK/SDIO
Drive the open collector ALERT output low.
•
Drop CS
•
•
Change LFDATA/CCLK/SDIO connected pin to output.
•
Clock in 16-bit SPI Read sequence.
•
Change LFDATA/CCLK/SDIO connected pin to input.
Raise CS to complete the SPI Read entry of command and address.
CS
To ensure no false clocks occur when CS drops.
SCLK/ALERT becomes SCLK input.
LFDATA/CCLK/SDIO becomes SDI input.
Driving SPI data.
Command, address and dummy data.
(output)
ALERT
The T
Configuration register data appears at 6th clock after T
LFDATA
(output)
1
CSH
(input)
(input)
SCLK
SDI
T
2
CSSC
is considered as one clock. Therefore, the
T
SPI Read Sequence.
SU
MSb
T
3
HD
4
16 Clocks for Read Command,
Address and Dummy Data
T
1/F
HI
SCLK
T
LO
CSH
LSb
.
T
SCCS
6
5
7.
8.
9.
10.
T
LFDATA
(output)
CS1
(output)
ALERT
T
Drop CS.
•
•
Clock out 16-bit SPI Read result.
•
•
•
Raise CS to complete the SPI Read.
Change SCLK/ALERT back to input.
CSH
T
CS0
AFE SCLK/ALERT becomes SCLK input.
LFDATA/CCLK/SDIO becomes SDO output.
First seven bits clocked-out are dummy bits.
Next eight bits are the Configuration register data.
The last bit is the Configuration register row parity bit.
(input)
(output)
SCLK
T
SDO
7
CSSC
8
16 Clocks for Read Result
© 2005 Microchip Technology Inc.
T
DO
T
CSSC
9
T
LFDATA
CS
(output)
(output)
ALERT
1
10
T
CSH
T
CS0