MCP2030-I/ST Microchip Technology, MCP2030-I/ST Datasheet - Page 44

• Manufacturer Part Number: MCP2030-I/ST
• Description: IC KEYLESS ENTRY AFE 14TSSOP
• Manufacturer: Microchip Technology

Specifications of MCP2030-I/ST

• Rf Type: ISM
• Frequency: 125kHz
• Features: 10kbps
• Package / Case: 14-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

MCP2030
5.30.2
When the carrier clock output is selected, the LFDATA
output is a square pulse of the input carrier clock and
available as soon as the AGC stabilization time (T
is completed. There are two Configuration register
options for the carrier clock output: (a) clock divide-by
one or (b) clock divide-by four, depending on bit
DATOUT<7> of Configuration Register 2 (Register 5-
3). The carrier clock output is available immediately
after the AGC settling time. The Output Enable Filter,
AGCSIG, and MODMIN options are applicable for the
carrier clock output in the same way as the demodu-
lated output. The input channel can be individually
enabled or disabled for the output. If more than one
channel is enabled, the output is the sum of each out-
put of all enabled channels. Therefore, the carrier clock
output waveform is not as precise as when only one
channel is enabled. It is recommended to enable one
channel only if a precise output waveform is desired.
There will be no valid output if all three channels are
disabled. See Figure 2-32 for carrier clock output
examples.
Related Configuration register bits:
• Configuration Register 1 (Register 5-2),
• Configuration Register 2 (Register 5-3),
• Configuration Register 0 (Register 5-1): all bits
• Configuration Register 5 (Register 5-6)
5.30.3
An analog current output is available at the RSSI pin
when the Received Signal Strength Indicator (RSSI)
output is selected by the Configuration register. The
analog current is linearly proportional to the input signal
strength.
All timers in the circuit, such as inactivity timer, alarm
timer, and AGC initialization time, are disabled during
the RSSI mode. Therefore, the RSSI output is not
affected by the AGC stabilization time, and available
immediately when the RSSI option is selected. The
device enters Active mode immediately when the RSSI
output is selected.
DS21981A-page 44
DATOUT <8:7>:
CLKDIV<7>:
are affected
bit 8 bit 7
0
0
1
1
0: Carrier Clock/1
1: Carrier Clock/4
CARRIER CLOCK OUTPUT
RECEIVED SIGNAL STRENGTH
INDICATOR (RSSI) OUTPUT
0: Demodulator Output
1: Carrier Clock Output
0: RSSI Output
1: RSSI Output
AGC
)
When the device receives an SPI command during the
RSSI output, the RSSI mode is temporary disabled
until the SPI communication is completed. It returns to
the RSSI mode again after the SPI communication is
completed. The RSSI mode is held until another
output type is selected (CS low turns off the RSSI
signal). To obtain the RSSI output for a particular input
channel, or to save operating power, the input channel
can be individually enabled or disabled. If more than
one channel is enabled, the RSSI output is from the
strongest signal channel. There will be no valid output
if all three channels are disabled.
The RSSI output current is linearly proportional to the
input signal strength. There are variations between
channel to channel and device to device. See
Figure 2-13 for examples. The linearity (ILR
the RSSI output current is tested by sampling the
outputs for three input points: 37 mV
and 370 mV
of input signal is compared with the expected output
current obtained from the line that is connecting the
two endpoints (37 mV
and Figure 5-7 show the details for the RSSI linearity
specification.
EQUATION 5-1:
FIGURE 5-7:
Example.
ILR
where,
Deviation at 100 mV
[I
signal.
I
that is connecting two endpoints (RSSI output currents
for 37 mV
RSSI
RSSI
y
RSSI
Deviation at 100 mV
I
expected = RSSI current obtained from the line
RSSI
measured - I
(%)
37 mV
PP
for 370 mV
PP
=
and 370 mV
. The RSSI output current for 100 mV
PP
d
Input Signal Amplitude
RSSI
100 mV
PP
PP
PP
RSSI LINEARITY
SPECIFICATION
RSSI Linearity Test
expected] at 100 mV
of Input Signal =
© 2005 Microchip Technology Inc.
PP
and 370 mV
of Input Signal
PP
PP
of Input Signal
of inputs).
y = a+bx
PP
370 mV
PP
). Equation 5-1
d = Deviation
, 100 mV
= Measured
= Expected
PP
x 100%
of input
PP
RSSI
) of
x
PP
PP
,