MPC8377EWLANA Freescale Semiconductor, MPC8377EWLANA Datasheet - Page 80

• Manufacturer Part Number: MPC8377EWLANA
• Description: ACCESS POINT/ROUTER MPC8377
• Manufacturer: Freescale Semiconductor

Specifications of MPC8377EWLANA

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

High-Speed Serial Interfaces (HSSI)
To illustrate these definitions using real values, consider the case of a CML (Current Mode Logic)
transmitter that has a common mode voltage of 2.25 V and each of its outputs, TD and TD, has a swing
that goes between 2.5 V and 2.0 V. Using these values, the peak-to-peak voltage swing of each signal (TD
or TD) is 500 mV
the differential signaling environment is fully symmetrical, the transmitter output’s differential swing
(V
between 500 mV and –500 mV, in other words, V
phase. The peak differential voltage (V
is 1000 mV
21.2
The SerDes reference clock inputs are applied to an internal PLL whose output creates the clock used by
the corresponding SerDes lanes. The SerDes reference clocks inputs are SD1_REF_CLK and
SD1_REF_CLK for both lanes of SerDes1, and SD2_REF_CLK and SD2_REF_CLK for both lanes of
SerDes2.
The following sections describe the SerDes reference clock requirements and some application
information.
21.2.1
Figure 52
80
OD
•
) has the same amplitude as each signal’s single-ended swing. The differential output signal ranges
A Volts
B Volts
SerDes Reference Clock Receiver Reference Circuit Structure
— The SDn_REF_CLK and SDn_REF_CLK are internally AC-coupled differential inputs as
— The external reference clock driver must be able to drive this termination.
SerDes Reference Clocks
shows a receiver reference diagram of the SerDes reference clocks.
shown in
50 Ω termination to SGND_SRDSn (xcorevss) followed by on-chip AC-coupling.
p-p
SerDes Reference Clock Receiver Characteristics
.
p-p
Figure 51. Differential Voltage Definitions for Transmitter or Receiver
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4
, which is referred as the single-ended swing for each signal. In this example, since
Figure
SDn_TX or
SDn_RX
SDn_TX or
SDn_RX
52. Each differential clock input (SDn_REF_CLK or SDn_REF_CLK) has a
Differential Peak-Peak Voltage, VDIFFpp = 2 × VDIFFp (not shown)
DIFFp
Differential Swing, VID or VOD = A – B
Differential Peak Voltage, VDIFFp = |A – B|
) is 500 mV. The peak-to-peak differential voltage (V
OD
is 500 mV in one phase and –500 mV in the other
Freescale Semiconductor
V
cm
= (A + B)/2
DIFFp-p
)