MPC8377EWLANA Freescale Semiconductor, MPC8377EWLANA Datasheet - Page 78

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MPC8377EWLANA

Manufacturer Part Number
MPC8377EWLANA
Description
ACCESS POINT/ROUTER MPC8377
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MPC8377EWLANA

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
High-Speed Serial Interfaces (HSSI)
Figure 49
Figure 50
21 High-Speed Serial Interfaces (HSSI)
The MPC8377E features two serializer/deserializer (SerDes) interfaces to be used for high-speed serial
interconnect applications. See
This section describes the common portion of SerDes DC electrical specifications, which is the DC
requirement for SerDes reference clocks. The SerDes data lane’s transmitter and receiver reference circuits
are also shown.
21.1
The SerDes utilizes differential signaling to transfer data across the serial link. This section defines terms
used in the description and specification of differential signals.
Figure 51
description. The figure shows waveform for either a transmitter output (SDn_TX and SDn_TX) or a
receiver input (SDn_RX and SDn_RX). Each signal swings between A volts and B volts where A > B.
78
Note: The clock edge is selectable on SPI.
Note: The clock edge is selectable on SPI.
SPICLK (output)
Signal Terms Definition
shows the SPI timing in slave mode (external clock).
shows the SPI timing in master mode (internal clock).
Output Signals:
shows how the signals are defined. For illustration purpose, only one SerDes lane is used for
Output Signals:
SPICLK (input)
Input Signals:
Input Signals:
(See Note)
(See Note)
(See Note)
(See Note)
SPIMISO
SPIMOSI
SPIMOSI
SPIMISO
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4
Figure 50. SPI AC Timing in Master Mode (Internal Clock) Diagram
Figure 49. SPI AC Timing in Slave Mode (External Clock) Diagram
t
NEIVKH
Table 1
t
NIIVKH
for the interfaces supported.
t
NIKHOV
t
NIIXKH
t
NEKHOV
tN
EIXKH
Freescale Semiconductor

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