EM250-RCM-R Ember, EM250-RCM-R Datasheet - Page 68

• Manufacturer Part Number: EM250-RCM-R
• Description: EM250 RCM BOARD
• Manufacturer: Ember
• Type: Transceiver, 802.15.4/ZigBeer

Specifications of EM250-RCM-R

• Frequency: 2.4GHz
• For Use With/related Products: EM250
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 636-1023

EM250
SC2_MODE [0x442A]
SC2_DATA [0x441E]
120-0082-000S
SC2_MODE
SC2_DATA
0-RW
0-R
0-R
0-R
15
15
0
0
0
7
7
(Re)start and stop segments are initiated by setting the register bits
SC2_I2CCTRL1
SC_I2CCMDFIN
For initiating a transmit segment, the data has to be written to the
ting the register bit
ternatively, the register bit
A receive segment is initiated by setting the register bit
until it clears, and then reading from the
in the
indicates if a NACK or ACK was received from an I
Interrupts are generated on the following events:
To generate interrupts to the CPU, the interrupt masks in the
abled.
5.3.3
0-RW
0-R
0-R
0-R
14
14
0
0
0
6
6
[1:0]
[7:0]
Bus command (
Character transmitted and slave device responded with NACK
Character transmitted (0 to 1 transition of
Character received (0 to 1 transition of
Received and lost character while receive FIFO was full (Receive overrun error)
Transmitted character while transmit FIFO was empty (Transmit underrun error)
SC2_I2CSTAT
Registers
SC2 Mode: 0 = disabled; 1 = disabled; 2 = SPI mode; 3 = I2C mode.
Note: To change between modes, the previous mode must be disabled first.
register, followed by waiting until they have cleared. Alternatively, the register bit
in the
0-RW
Transmit and receive data register. Writing to this register pushes a byte onto the transmit
FIFO. Reading from this register pulls a byte from the receive FIFO.
0-R
0-R
0-R
13
13
0
0
5
0
5
SC_I2CSTART/SC_I2CSTOP
SC_I2CSEND
can be used for waiting. Now the register bit
SC2_I2CSTAT
SC_I2CTXFIN
in the
0-RW
0-R
0-R
0-R
12
12
0
0
4
0
4
can be used for waiting.
SC2_DATA
SC2_I2CCTRL1
SC2_DATA
in the
SC_I2CRXFIN
Page 68
) completed (0 to 1 transition of
SC_I2CTXFIN
SC2_I2CSTAT
2
C slave device.
0-RW
0-R
0-R
0-R
11
11
0
0
3
0
3
data register. Alternatively, the register bit
register, and completed by waiting until it clears. Al-
SC_I2CRECV
)
)
INT_SC2CFG
can be used for waiting.
SC_I2CRXNAK
0-RW
SC2_DATA
0-R
0-R
0-R
10
10
SC_I2CSTART
0
0
2
0
2
in the
and
SC2_I2CCTRL1
data register, followed by set-
INT_CFG
SC_I2CCMDFIN
in the
or
0-RW
0-RW
0-R
0-R
9
0
1
9
0
1
SC_I2CSTOP
SC2_I2CSTAT
register must be en-
SC2_MODE
register, waiting
)
SC_I2CRXFIN
in the
0-RW
0-RW
0-R
0-R
register
0
0
8
0
8
0