4320-DKDB2 Silicon Laboratories Inc, 4320-DKDB2 Datasheet - Page 16

• Manufacturer Part Number: 4320-DKDB2
• Description: KIT DEV TEST EZRADIO SI4320 RX
• Manufacturer: Silicon Laboratories Inc

Specifications of 4320-DKDB2

• Accessory Type: Test Card, Receiver, 434MHz
• Wireless Frequency: 434 MHz
• Interface Type: SPI
• Modulation: FSK, OOK
• For Use With/related Products: EZRadio®
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

In automatic operation mode (no strobe signal is needed from the microcontroller to update the output offset register), the AFC circuit is
automatically enabled when VDI indicates a potential incoming signal during the whole measurement cycle and the circuit measures the
same result in two subsequent cycles.
There are three operation modes, example from the possible application:
1, (a1=0, a0=1) The circuit measures the frequency offset only once after power up. This way, the extended TX/RX maximum distance can
be achieved. Possible usage: In the final application when the user is inserted the battery the circuit measures and compensate the
frequency offset caused by the crystal tolerances. This method enables to use cheaper quartz in the application and provide quite good
protection against locking in an interferer.
2a, (a1=1, a0=0) The circuit measures automatically the frequency offset during an initial low data rate pattern –easier to receive- (i.e.:
00110011) of the package and change the receiving frequency according that. The further part of the package can be received by the
corrected frequency settings.
2b, (a1=1, a0=0) The transmitter must transmit the first part of the packet with a step higher deviation and later there is a possibility to
reduce it.
In both cases (2a and 2b) when the VDI indicates poor receiving conditions (VDI goes low) the output register is automatically cleared. It’s
suggested to use when one receiver receives signal from more than one transmitter.
3, (a1=1, a0=1) It is similar to the 2a and 2b modes, but 3 is suggested to use when a receiver operates with only one transmitter. After a
complete measuring cycle, the measured value is held independently of the sate of VDI signal.
8. Data Filter Command
Bit 7 <al>:
Bit 6 <ml>:
Bit 3-4 <s0 : s1>:
OOK to filter: the analog RSSI signal is used as received data. The DRSSI threshold level is used for slicing.
Digital: this is a digital realization of an analog RC filter followed by a comparator with hysteresis. The time constant is automatically
adjusted to the bit rate defined by the Data Rate Command.
Analog RC filter: The demodulator output is fed to pin 7 over a 10 kOhm resistor. The filter cut-off frequency is set by the external capacitor
connected to this pin and VSS.
The table shows the optimal filter capacitor values for different data rates:
Note:
Bit 0-2 <f0 : f2>:
Note:
bit
15
1
1.2 kbps
If analog RC filter is selected the internal clock recovery circuit and the FIFO cannot be used.
To let the DQD report "good signal quality" the threshold parameter should be less than 4 in the case when the bitrate is close to
the deviation. At higher deviation/bitrate settings higher threshold parameter can report "good signal quality" as well.
12 nF
14
1
DQD threshold parameter.
Clock recovery (CR) auto lock control if set.
It means that the CR start in fast mode after locking it automatically switches to slow mode.
Clock recovery lock control
1: fast mode, fast attack and fast release
0: slow mode, slow attack and slow release
Using the slower one requires more accurate bit timing (see Data Rate Command).
Select the type of the data filter:
13
0
2.4 kbps
8.2 nF
12
0
11
0
4.8 kbps
6.8 nF
10
1
9
0
s1
0
0
1
1
9.6 kbps
8
0
3.3 nF
s0
0
1
0
1
al
7
OOK to filter
Digital filter
Reserved
Analog RC filter
ml
6
19.2 kbps
1.5 nF
Filter Type
5
1
s1
4
38.4 kbps
680 pF
s0
3
f2
2
57.6 kbps
270 pF
f1
1
f0
0
115.2 kbps
150 pF
C42Ch
POR
256 kbps
100 pF
Si4320
16