4320-DKDB2 Silicon Laboratories Inc, 4320-DKDB2 Datasheet - Page 11

• Manufacturer Part Number: 4320-DKDB2
• Description: KIT DEV TEST EZRADIO SI4320 RX
• Manufacturer: Silicon Laboratories Inc

Specifications of 4320-DKDB2

• Accessory Type: Test Card, Receiver, 434MHz
• Wireless Frequency: 434 MHz
• Interface Type: SPI
• Modulation: FSK, OOK
• For Use With/related Products: EZRadio®
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

CONTROL INTERFACE
Commands to the receiver are sent serially. Data bits on pin SDI are shifted into the device upon the rising edge of the clock on pin SCK
whenever the chip select pin nSEL is low. When the nSEL signal is high, it initializes the serial interface. The number of bits sent is an integer
multiple of 8. All commands consist of a command code, followed by a varying number of parameter or data bits. All data are sent MSB first
(e.g. bit 15 for a 16-bit command). Bits having no influence (don’t care) are indicated with X. The Power On Reset (POR) circuit sets default
values in all control registers.
The status information or received data can be read serially over the SDO pin. Bits are shifted out upon the falling edge of CLK signal. When
the nSEL is high, the SDO output is in a high impedance state.
The receiver will generate an interrupt request (IRQ) for the microcontroller on the following events:
FFIT and FFOV are applicable only when the FIFO is enabled. To find out why the nIRQ was issued, the status bits should be read out.
Timing Specification
Timing Diagram




nIRQ
nSEL
SDI
SCK
Symbol
Supply voltage below the preprogrammed value is detected (LBD)
Wake-up timer timeout (WK-UP)
FIFO received the preprogrammed amount of bits (FFIT)
FIFO overflow (FFOV)
t
t
t
t
t
t
t
t
SHI
OD
CH
CL
SS
SH
DS
DH
t
S S
t
DS
BIT 15
t
Parameter
Clock high time
Clock low time
Select setup time (nSEL falling edge to SCK rising edge)
Select hold time (SCK falling edge to nSEL rising edge)
Select high time
Data setup time (SDI transition to SCK rising edge)
Data hold time (SCK rising edge to SDI transition)
Data delay time
CH
t
DH
t
CL
BIT 14
BIT 13
BI T 8
t
OD
POR
BI T 7
W K-UP
BIT 1
Minimum value [ns]
nIRQ
BI T 0
25
25
10
10
25
10
t
SH
5
5
t
SHI
Si4320
11