DK-DEV-4SGX530N Altera, DK-DEV-4SGX530N Datasheet - Page 46

• Manufacturer Part Number: DK-DEV-4SGX530N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IV GXr
• Type: FPGAr

Specifications of DK-DEV-4SGX530N

• Contents: Board, Cable, Documentation, Power Supply
• For Use With/related Products: Stratix® IV GX
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2714

6–22
The Clock Control
Stratix IV GX FPGA Development Kit User Guide
Calculating Power
f
■
■
Reset
This Reset control clears the graph, resets the minimum and maximum values, and
restarts the Power Monitor.
The Power Monitor calculates power by measuring two different voltages with the
LT2418 A/D and applying the equation P = V × I to determine the power
consumption. The LT2418 measures the voltage after the appropriate sense resistor
(Vsense) and the voltage drop across that sense resistor (Vdif). The current (I) is
calculated by dividing the measured voltage drop across the resistor by the value of
the sense resistor (I = Vdif/R). Through substitution, the equation for calculating
power becomes P = V × I = Vsense × (Vdif/R) = (Vsense) × (Vdif) × (1/.003).
You can verify the power numbers shown in the Power Monitor with a digital
multimeter that is capable of measuring microvolts to ensure you have enough
significant digits for an accurate calculation. Measure the voltage on one side of the
resistor (the side opposite the power source) and then measure the voltage on the
other side. The first measurement is Vsense and the difference between the two
measurements is Vdif. Plug the values into the equation to determine the power
consumption.
The Clock Control application sets the Si570 programmable oscillator to any
frequency between 10 MHz and 810 MHz with eight digits of precision to the right of
the decimal point. The oscillator drives a 2-to-4 buffer that drives a copy of the clock
to all four edges of the FPGA.
The Clock Control application runs as a stand-alone application. ClockControl.exe
resides in the <install
dir>\kits\stratixIVGX_4sgx230_fpga\examples\board_test_system directory. On
Windows, click Start > All Programs > Altera > Stratix IV GX FPGA Development
Kit <version> > Clock Control to start the application.
For more information about the Si570 and the Stratix IV GX FPGA development
board’s clocking circuitry and clock input pins, refer to the
Development Board Reference
Scale select—Specifies the amount to scale the power graph. Select a smaller
number to zoom in to see finer detail. Select a larger number to zoom out to see the
entire range of recorded values.
Update speed—Specifies how often to refresh the graph.
Manual.
Stratix IV GX FPGA
August 2010 Altera Corporation
Chapter 6: Board Test System
The Clock Control