DK-DEV-4SGX530N Altera, DK-DEV-4SGX530N Datasheet - Page 39

• Manufacturer Part Number: DK-DEV-4SGX530N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IV GXr
• Type: FPGAr

Specifications of DK-DEV-4SGX530N

• Contents: Board, Cable, Documentation, Power Supply
• For Use With/related Products: Stratix® IV GX
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2714

Chapter 6: Board Test System
Using the Board Test System
August 2010 Altera Corporation
The following sections describe the controls on the HSMC tab.
Status
The Status control displays the following status information during the loopback test:
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Port
The Port control allows you to specify the type of test to run on the HSMC ports. The
following HSMC port tests are available:
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Data Type
The Data type control specifies the type of data contained in the transactions. The
following data types are available for analysis:
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Error Control
The Error control controls display data errors detected during analysis and allow you
to insert errors:
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PLL lock—Shows the PLL locked or unlocked state.
Channel lock—Shows the channel locked or unlocked state. When locked, all
lanes are word aligned and channel bonded.
Pattern sync—Shows the pattern synced or not synced state. The pattern is
considered synced when the start of the data sequence is detected.
HSMA x4 Tranceivers [0..3]
HSMA x4 Tranceivers [4..7]
HSMB x4 Tranceivers [0..3]
HSMB x2 Tranceivers [4..5]
HSMA x17 LVDS SERDES
HSMB x17 LVDS SERDES
HSMA x3 Single Ended Loopback
HSMB x3 Single Ended Loopback
PRBS—Selects pseudo-random bit sequences.
Memory—Selects a generic data pattern stored in the on chip memory of the
Stratix IV GX device.
Math—Selects data generated from a simple math function within the FPGA
fabric.
Detected errors—Displays the number of data errors detected in the hardware.
Inserted errors—Displays the number of errors inserted into the transmit data
stream.
Insert Error—Inserts a one-word error into the transmit data stream each time you
click the button. Insert Error is only enabled during transaction performance
analysis.
Clear—Resets the Detected errors and Inserted errors counters to zeros.
Stratix IV GX FPGA Development Kit User Guide
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