DK-DEV-4SGX530N Altera, DK-DEV-4SGX530N Datasheet - Page 33

• Manufacturer Part Number: DK-DEV-4SGX530N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IV GXr
• Type: FPGAr

Specifications of DK-DEV-4SGX530N

• Contents: Board, Cable, Documentation, Power Supply
• For Use With/related Products: Stratix® IV GX
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2714

Chapter 6: Board Test System
Using the Board Test System
August 2010 Altera Corporation
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SRAM
The SRAM control allows you to read and write the SRAM on your board. Type a
starting address in the text box and click Read. Values starting at the specified address
appear in the table. The SRAM addresses display in the format the Nios II processor
within the FPGA uses, that is, each SRAM address is offset by 0x00400000. Thus, the
first location in SRAM appears as 0x00400000 in the GUI.
If you enter an address outside of the 0x00400000 to 0x005FFFFF SRAM address
space, a warning message identifies the valid SRAM address range.
To update the SRAM contents, change values in the table and click Write. The
application writes the new values to SRAM and then reads the values back to
guarantee that the graphical display accurately reflects the memory contents.
Flash
The Flash control allows you to read and write the flash memory on your board. Type
a starting address in the text box and click Read. Values starting at the specified
address appear in the table. The flash memory addresses display in the format the
Nios II processor within the FPGA uses, that is, each flash memory address is offset
by 0x04000000. Thus, the first location in flash memory appears as 0x04000000 in the
GUI.
If you enter an address outside of the 0x04000000 to 0x07FFFFFF flash memory
address space, a warning message identifies the valid flash memory address range.
To update the flash memory contents, change values in the table and click Write. The
application writes the new values to flash memory and then reads the values back to
guarantee that the graphical display accurately reflects the memory contents.
To prevent overwriting the dedicated portions of flash memory, the application limits
the writable flash memory address range from 0x07FE0000 to 0x07FFFFFF (which
corresponds to the unused flash memory address range of 0x03FE0000 - 0x03FFFFFF
shown in
Figure 6–1 on page 6–2
and
Table A–1 on page
Stratix IV GX FPGA Development Kit User Guide
A–1).
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