XR17D158IV-F Exar Corporation, XR17D158IV-F Datasheet
XR17D158IV-F
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XR17D158IV-F Summary of contents
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AUGUST 2005 GENERAL DESCRIPTION 1 The XR17D158 (D158 octal PCI Bus Universal Asynchronous Receiver and Transmitter (UART) with support for PCI Bus universal VIO buffers in the same package and pin-out as the XR17C158, XR17C154 and XR17D154. ...
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... AD31 139 AD30 140 AD29 AD28 141 AD27 142 AD26 143 144 AD25 ORDERING INFORMATION ART UMBER ACKAGE XR17D158CV 144-Lead LQFP XR17D158IV 144-Lead LQFP XR17D158 PERATING EMPERATURE ANGE 0°C to +70°C -40°C to +85° REV. 1.2.2 72 CTS5# 71 RX5 ENIR 70 69 TMRCK ...
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REV. 1.2.2 PIN DESCRIPTIONS AME IN PCI LOCAL BUS INTERFACE RST# 134 CLK 135 AD31-AD25, 138-144, AD24, 1, AD23-AD16, 6-13, AD15-AD8, 26-33, AD7-AD0 37-44 FRAME# 15 C/BE0#- 36,25,14,2 C/BE3# IRDY# 16 TRDY# 17 STOP# 21 ...
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XR17D158 UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART PIN DESCRIPTIONS AME IN RI0# 128 TX1 117 RX1 124 RTS1# 119 CTS1# 123 DTR1# 118 DSR1# 122 CD1# 121 RI1# 120 TX2 106 RX2 99 RTS2# ...
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REV. 1.2.2 PIN DESCRIPTIONS AME IN RTS4# 86 CTS4# 82 DTR4# 87 DSR4# 83 CD4# 84 RI4# 85 TX5 80 RX5 71 RTS5# 78 CTS5# 72 DTR5# 79 DSR5# 75 CD5# 76 RI5# 77 TX6 ...
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XR17D158 UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART PIN DESCRIPTIONS AME IN CD7# 50 RI7# 51 ANCILLARY SIGNALS MPIO0 108 I/O MPIO1 107 I/O MPIO2 74 I/O MPIO3 73 I/O MPIO4 68 I/O MPIO5 67 ...
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REV. 1.2.2 PIN DESCRIPTIONS AME IN VIO 4, 19, 34, 45, 137 GND 5,20,35,46,63, 89,136 N : Pin type: I=Input, O=Output, IO= Input/output, OD=Output Open Drain. OTE UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART ...
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XR17D158 UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART FUNCTIONAL DESCRIPTION The XR17D158 (D158) integrates the functions of 8 enhanced 16550 UARTs with the PCI Local Bus interface and a non-volatile memory interface for PCI bus’s plug-and-play auto-configuration, a 16-bit ...
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REV. 1.2.2 1.0 APPLICATION EXAMPLES The XR17D158 is designed to operate with VCC (voltage to the UART Core Logic only, irrespective of whether the PCI bus is at 3.3V or 5V. Voltage, VIO that can be used ...
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XR17D158 UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART IGURE YPICAL PPLICATIONS IN AN Exam ple 1 VIO = 3.3V, VCC = 5V Exam ple 2 VIO = 5V, VCC = MBEDDED YSTEM ...
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REV. 1.2.2 2.0 XR17D158 REGISTERS The XR17D158 UART has three different sets of registers as shown in configuration space registers are for plug-and-play auto-configuration when connecting the device to a the PCI bus. This auto-configuration feature makes installation very ...
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XR17D158 UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART T 2: PCI L ABLE DDRESS ITS YPE 0x00 31:16 Device ID (Exar device ID number) 1 RWR 15:0 Vendor ID (Exar) specified by PCISIG 1 RWR 0x04 ...
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REV. 1.2 PCI L ABLE DDRESS ITS YPE 0x2C 31:16 1 Subsystem ID (write from external EEPROM by customer) RWR 15:0 1 Subsystem Vendor ID (write from external EEPROM by cus- RWR tomer) 0x30 ...
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XR17D158 UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART T 3: XR17D158 D ABLE FFSET DDRESS EMORY PACE 0x000 - 0x00F UART channel 0 Regs 0x010 - 0x07F Reserved 0x080 - 0x093 DEVICE CONFIG. REGISTERS 0x094 ...
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REV. 1.2 XR17D158 D ABLE FFSET DDRESS EMORY PACE 0x740 - 0x77F Reserved 0x780 - 0x7FF UART 3 – Read FIFO with errors 0x800 - 0x80F UART channel 4 Regs 0x810 - 0x8FF ...
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XR17D158 UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART T 3: XR17D158 D ABLE FFSET DDRESS EMORY PACE 0xF40 - 0xF7F Reserved 0xF80 - 0xFFF UART 7 – Read FIFO with errors C R EVICE ONFIGURATION ...
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REV. 1.2 ABLE EVICE A [A7:A0] R DDRESS EGISTER Ox080 INT0 [7:0] Ox081 INT1 [15:8] Ox082 INT2 [23:16] Ox083 INT3 [31:24] Ox084 TIMERCNTL Ox085 TIMER Ox086 TIMERLSB Ox087 TIMERMSB Ox088 8XMODE Ox089 REGA Ox08A RESET Ox08B ...
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XR17D158 UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART 2.2.1 The Interrupt Status Register The XR17D158 has a 32-bit wide register [INT0, INT1, INT2 and INT3] to provide interrupt information and supports two interrupt schemes. The first scheme uses an ...
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REV. 1.2 IGURE HE LOBAL NTERRUPT INT3 Register Channel-7 Channel-6 Channel-5 Bit Bit Bit Bit Bit Bit Bit Bit N+2 N+1 N N+2 N+1 N N+2 N UART C ABLE P ...
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XR17D158 UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART 2.2.2 General Purpose 16-bit Timer/Counter [TIMERMSB, TIMELSB, TIMER, TIMECNTL XX-XX-00-00 16-bit down-count timer for general purpose timer or counter. Its clock source may be selected from internal ...
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REV. 1.2.2 TIMERMSB [31:24] and TIMERLSB [23:16] TIMERMSB and TIMERLSB form a 16-bit value. The least-significant bit of the timer is being bit [0] of the TIMERLSB with most-significant-bit being bit [7] in TIMERMSB. Notice that these registers do ...
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XR17D158 UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART 2.2.6 SLEEP [31:24] (default 0x00) Each UART can be separately enabled to enter Sleep mode through the Sleep register. Sleep mode reduces power consumption when the system needs to put the ...
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REV. 1.2.2 DVID [15:8] Device identification for the type of UART. The upper nibble indicates XR17Dxxx series with lower nibble indicating the number of channels. Examples: XR17C158 or XR17D158 = 0x28 XR17C154 or XR17D154 = 0x24 ...
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XR17D158 UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART IGURE ULTIPURPOSE INPUT MPIOINT [7:0] INT AND MPIOLVL [7:0] Read Input Level MPIOINV [7:0] (Input Inversion Enable =1) MPIOLVL [7:0] (Output Level) MPIO3T [7:0] (3-state Enable =1) MPIOSEL ...
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REV. 1.2.2 MPIO3T [7:0] (default 0x00) Output pin tri-state control. A logic 0 (default) sets the output to active level per register MPIOBIT settling, a logic 1 sets the output pin to tri-state. MPIOINV [7:0] (default 0x00) Input inversion ...
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XR17D158 UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART 3.0 CRYSTAL OSCILLATOR / BUFFER The D158 includes an on-chip oscillator (XTAL1 and XTAL2). The crystal oscillator provides the system clock to the Baud Rate Generators (BRG) in each of the ...
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REV. 1.2.2 4.0 TRANSMIT AND RECEIVE DATA There are two methods to load transmit data and unload receive data from each UART channel. First, there is a transmit data register and receive data register for each UART channel in ...
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XR17D158 UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART Channel ReceiveData in 32-bit alignment through the Configuration Register Address 0x0100, 0x0300, 0x0500, 0x0700, 0x0900, 0x0B00, 0x0D00 and 0x0F00 Receive Data Byte n ...
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REV. 1.2.2 Channel Transmit Data in 32-bit alignment through the Configuration Register Address 0x0100, 0x0300, 0x0500, 0x0700, 0x0900, 0x0B00, 0x0D00 and 0x0F00 Transmit Data Byte n ...
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XR17D158 UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART 5.0 UART There are 8 UARTs [channels 7:0] in the D158. Each has its own 64-byte of transmit and receive FIFO, a set of 16550 compatible control and status registers, and ...
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REV. 1.2.2 T 10: T ABLE YPICAL DATA RATES WITH A O Data Rate O Data Rate UTPUT UTPUT MCR Bit-7=1 MCR Bit-7=0 100 400 600 2400 1200 4800 2400 9600 4800 19.2k 9600 38.4k 19.2k 76.8k 38.4k 153.6k ...
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XR17D158 UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART F 12 IGURE RANSMITTER PERATION IN NON Data Byte 16X or 8X Clock (8XMODE Register) Transmit Shift Register (TSR) 5.2.3 Transmitter Operation in FIFO mode The host may fill ...
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REV. 1.2.2 5.3 Receiver The receiver section contains an 8-bit Receive Shift Register (RSR) and Receive Holding Register (RHR). The RSR uses the 16X or 8X clock for timing. It verifies and validates every bit on the incoming character ...
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XR17D158 UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART 5.3.3 Receiver Operation with FIFO F 15 IGURE ECEIVER PERATION IN 16X or 8X Sampling Clock (8XMODE Reg.) Receive Data Shift Register (RSR) 64 bytes by 11- bit wide ...
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REV. 1.2.2 Two interrupts associated with auto RTS/CTS and DTR/DSR flow control have been added to give indication when RTS#/DTR# pin or CTS#/DSR# pin are de-asserted during operation. These interrupts are enabled by: • Setting EFR bit ...
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XR17D158 UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART 5.5 Infrared Mode Each UART in the D158 includes the infrared encoder and decoder compatible to the IrDA (Infrared Data Association) version 1.0. The input pin ENIR conveniently activates all 8 ...
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REV. 1.2.2 5.6 Internal Loopback Each UART channel provides an internal loopback capability for system diagnostic. The internal loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally. Figure 18 shows ...
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XR17D158 UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART 5.7 UART CHANNEL CONFIGURATION REGISTERS AND ADDRESS DECODING The 8 sets of UART configuration registers are decoded using address lines A8 to A11 as shown below. Address lines ...
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REV. 1.2.2 T 12: UART CHANNEL CONFIGURATION REGISTERS ABLE A DDRESS TXTRG - Transmit FIFO Trigger Level RXCNT - Receive FIFO Level Counter RXTRG - Receive FIFO ...
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XR17D158 UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART T 13: UART CHANNEL CONFIGURATION REGISTERS DESCRIPTION. ABLE DDRESS EG EAD A3- AME RITE SPR R/W Bit-7 1 ...
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REV. 1.2.2 5.8.4 Interrupt Enable Register (IER) - Read/Write The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status and modem status registers. These interrupts are reported in the Interrupt Status Register (ISR) ...
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XR17D158 UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART IER[4]: Reserved IER[5]: Xoff Interrupt Enable (requires EFR bit-4=1) • Logic 0 = Disable the software flow control, receive Xoff interrupt (default). • Logic 1 = Enable the software flow control, ...
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REV. 1.2 ABLE P ISR R RIORITY EGISTER EVEL ...
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XR17D158 UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART FCR[2]: TX FIFO Reset This bit is only active when FCR bit-0 is active. • Logic transmit FIFO reset (default). • Logic 1 = Reset the transmit FIFO ...
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REV. 1.2.2 FCR[7:6]: Receive FIFO Trigger Select (logic 0 = default, RX trigger level =1) The FCTR Bits 6-7 are associated with these 2 bits. These 2 bits are used to set the trigger level for the receiv- er ...
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XR17D158 UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART 5.8.7 Line Control Register (LCR) - Read/Write The Line Control Register is used to specify the asynchronous data communication format. The word or character length, the number of stop bits, and ...
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REV. 1.2.2 LCR B -5 LCR LCR[6]: Transmit Break Enable When enabled the Break control bit causes a break condition to be transmitted (the TX output is forced to a “space", LOW ...
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XR17D158 UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART MCR[5]: Xon-Any Enable • Logic 0 = Disable Xon-Any function (for 16C550 compatibility) (default). • Logic 1 = Enable Xon-Any function. In this mode any RX character received will enable Xon, ...
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REV. 1.2.2 LSR[5]: Transmit Holding Register Empty Flag This bit is the Transmit Holding Register Empty indicator. This bit indicates that the transmitter is ready to accept a new character for transmission. In addition, this bit causes the UART ...
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XR17D158 UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART MSR[5]: DSR Input Status This input may be used for auto DTR/DSR flow control function, see (RTS/CTS or DTR/DSR) Flow Control Operation” on page 34 flow control is not used, this ...
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REV. 1.2.2 5.8.12 SCRATCH PAD REGISTER (SPR) - Read/Write This is an 8-bit general purpose register for the user to store temporary data. The content of this register is preserved during sleep mode but becomes 0xFF (default) after a ...
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XR17D158 UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART T 18 ABLE ELECTABLE FCTR B -3 FCTR ...
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REV. 1.2.2 EFR[4]: Enhanced Function Bits Enable Enhanced function control bit. This bit enables the functions in IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and MCR bits 5 modified. After modifying any enhanced bits, EFR ...
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XR17D158 UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART EFR[6]: Auto RTS or DTR Flow Control Enable RTS#/DTR# output may be used for hardware flow control by setting EFR bit-6 to logic 1. When Auto RTS/ DTR is selected, an ...
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REV. 1.2.2 REGISTERS DLL DLM RHR THR IER FCR ISR LCR MCR LSR MSR SPR FCTR EFR TXCNT TXTRG RXCNT RXTRG XCHAR XON1 XON2 XOFF1 XOFF2 I/O SIGNALS TX[ch-7:0] RTS#[ch-7:0] DTR#[ch-7:0] EECK EECS EEDI UNIVERSAL (3.3V AND 5V) PCI ...
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XR17D158 UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART 6.0 PROGRAMMING EXAMPLES 6 NLOADING ECEIVE ATA It is suggested that before starting to read the Special Receive FIFO Data with Status to unload data from any ...
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REV. 1.2.2 ABSOLUTE MAXIMUM RATINGS Power Supply Range Voltage at Any Pin Operating Temperature Storage Temperature Package Dissipation Thermal Resistance (20x20x1.4mm 144-LQFP) ELECTRICAL CHARACTERISTICS DC ELECTRICAL CHARACTERISTICS FOR 5V PCI BUS INTERFACE (VIO = 4.75-5.25V, VCC = 4.5-5.5V), TA=0 ...
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XR17D158 UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART AC ELECTRICAL CHARACTERISTICS FOR 5V PCI BUS INTERFACE (VIO = 4.75-5.25V, VCC = 4.5 - 5.5V), TA YMBOL ARAMETER XTAL1 UART Crystal Oscillator ECLK External Clock T External Clock ...
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REV. 1.2.2 DC ELECTRICAL CHARACTERISTICS FOR 3.3V PCI BUS INTERFACE (VIO = 3.0-3.6V, VCC = 4.5 - 5.5V), TA YMBOL ARAMETER V Input Low Voltage IL V Input Low Voltage IL V Input High Voltage IH V ...
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XR17D158 UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART AC ELECTRICAL CHARACTERISTICS FOR 3.3V PCI BUS INTERFACE (VIO = 3.0-3.6V, VCC = 4.5 - 5.5V), TA YMBOL ARAMETER XTAL1 UART Crystal Oscillator ECLK External Clock T External Clock ...
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REV. 1.2 IGURE IMING OR XTERNAL 2V External Clock 0.8V UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART C I XTAL1 P LOCK NPUT ECLK T ECH 61 XR17D158 T ECL ...
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XR17D158 UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART F 20. PCI B C IGURE US ONFIGURATION CLK Host FRAME# Host AD[31:0] Host Target C/BE[3:0]# Host IRDY# Host TRDY# Target DEVSEL# Target CLK Host FRAME# Host AD[31:0] Host Target C/BE[3:0]# ...
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REV. 1.2 IGURE EVICE ONFIGURATION AND CLK Host 1 2 FRAME# Host AD[31:0] Address Host Target Bus C/BE[3:0]# Byte Enable# = BYTE CMD Host IRDY# Host TRDY# Target DEVSEL# Target Address PAR Parity Host Target ...
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XR17D158 UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART F 22 IGURE EVICE ONFIGURATION REGISTERS TION CLK Host FRAME# Host Data AD[31:0] Address DWORD Host Target Bus C/BE[3:0]# Byte Enable# = DWORD CMD Host IRDY# ...
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REV. 1.2 IGURE EVICE ONFIGURATION CLK Host 1 FRAME# Host AD[31:0] AD Host Target C/BE[3:0]# Bus Byte Enable# = DWORD CMD Host IRDY# Host TRDY# Target DEVSEL# Target PAR AD Host Target PERR# Target SERR# ...
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XR17D158 UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART F 24. 5V PCI B C (DC IGURE US LOCK 4 nSec (max) CLK Tvalid (2-11 nSec) Bused Signal Output Delay Ton (2 nSec min) Tri-State Output Bused Signal Input 33MH ...
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REV. 1.2.2 F 25. 3.3V PCI B C (DC IGURE US LOCK 1.44 ns (max) CLK Tvalid (2-11 ns) Bused Signal Output Delay Ton (2 ns min) Tri-State Output Bused Signal Input UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL ...
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XR17D158 UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART F 26 IGURE RANSMIT ATA NTERRUPT AT START BIT TX Data TX Interrupt at Transmit Trigger Level F 27 IGURE ECEIVE ATA EADY START BIT ...
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REV. 1.2.2 PACKAGE DIMENSIONS 108 109 144 1 A Seating Plane Note: The control dimension is the millimeter column OTE SYMBOL α UNIVERSAL (3.3V AND 5V) ...
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... August 2005 1.2.2 EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’ ...
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REV. 1.2.2 GENERAL DESCRIPTION................................................................................................. 1 A ............................................................................................................................................... 1 PPLICATIONS F ..................................................................................................................................................... 1 EATURES ............................................................................................................................................................. 1 IGURE LOCK IAGRAM .................................................................................................................................................. 2 IGURE THE EVICE ................................................................................................................................ 2 ORDERING INFORMATION ...
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XR17D158 5V PCI BUS OCTAL UART 5.2.3 TRANSMITTER OPERATION IN FIFO MODE ........................................................................................................... 32 5.2.4 AUTO RS485 OPERATION ........................................................................................................................................ IGURE RANSMITTER PERATION IN 5.3 RECEIVER ...................................................................................................................................................... 33 5.3.1 RECEIVE HOLDING REGISTER (RHR) .................................................................................................................... 33 5.3.2 ...
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REV. 1.2.2 PACKAGE DIMENSIONS ................................................................................................ ...................................................................................................................................... 70 EVISION ISTORY T C ............................................................................................................ I ABLE OF ONTENTS 5V PCI BUS OCTAL UART III XR17D158 ...