XR17D154IV-F Exar Corporation, XR17D154IV-F Datasheet - Page 16

IC UART PCI BUS QUAD 144LQFP

XR17D154IV-F

Manufacturer Part Number
XR17D154IV-F
Description
IC UART PCI BUS QUAD 144LQFP
Manufacturer
Exar Corporation
Type
IrDA or RS- 485r
Datasheet

Specifications of XR17D154IV-F

Number Of Channels
4, QUART
Package / Case
144-LQFP
Features
*
Fifo's
64 Byte
Protocol
RS485
Voltage - Supply
3.3V, 5V
With Auto Flow Control
Yes
With Irda Encoder/decoder
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
Mounting Type
Surface Mount
Data Rate
6.25 Mbps
Supply Voltage (max)
5.5 V
Supply Voltage (min)
3 V
Supply Current
4 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Operating Supply Voltage
3.3 V or 5 V
No. Of Channels
4
Uart Features
Tx/Rx FIFO Counters
Supply Voltage Range
3V To 5.5V
Operating Temperature Range
-40°C To +85°C
Digital Ic Case Style
LQFP
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
1016-1290

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XR17D154
UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART
Registers INT3, INT2 and INT1 [32:8]
Twenty four bit encoded interrupt indicator. Each channel’s interrupt is encoded into 3 bits for receive, transmit,
and status. Bit [10:8] represent channel 0 and go up to channel 3 with bits [19:17]. The 3 bit encoding and their
priority order are shown below in
exist within channel 0 space (bits [10:8]) only.
.
F
P
IGURE
RIORITY
N+2
Bit
x
1
2
3
4
5
6
7
Rsvd
N+1
Bit
6. T
B
Bit
N
HE
IT
[
INT3 Register
0
0
0
0
1
1
1
1
N
G
N+2
Bit
+2]
LOBAL
Rsvd
N+1
Bit
B
IT
I
T
Bit
N
[
NTERRUPT
0
0
1
1
0
0
1
1
N
ABLE
+1]
N+2
Bit
6: UART C
Rsvd
B
N+1
Bit
Table
IT
0
1
0
1
0
1
0
1
[
R
N
EGISTER
Bit
]
N
None
RXRDY and RX Line Status (logic OR of LSR[4:1])
RXRDY Time-out
TXRDY, THR or TSR (auto RS485 mode) empty
MSR, RTS/CTS or DTR/DSR delta or Xoff/Xon det. or special char. detected
Reserved.
MPIO pin(s). Available only within channel 0, reserved in other channels.
TIMER Time-out. Available only within channel 0, reserved in other channels.
6. The Timer and MPIO interrupts are for the device and therefore they
N+2
Bit
HANNEL
Rsvd
INT0, INT1, INT2 and INT3
, INT0, INT1, INT2
N+1
Bit
Interrupt Registers,
INT2 Register
Bit
N
[3:0] I
N+2
Bit
16
Channel-3
NTERRUPT
N+1
Bit
Bit
N
AND
I
NTERRUPT
N+2
Bit
S
Channel-2
INT3
OURCE
Rsvd
N+1
Bit-7
Bit
Rsvd Rsvd
Bit-6
Bit
N
S
E
OURCE
NCODING
Bit-5
N+2
Bit
Channel-1
INT0 Register
Rsvd
Bit-4
(
N+1
INT1 Register
Bit
S
)
Ch-3 Ch-2 Ch-1 Ch-0
Bit-3
Bit
N
N+2
Bit-2
Bit
xr
Channel-0
N+1
Bit-1
Bit
Bit-0
Bit
N
REV. 1.2.2

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