MC9328MX1DVM20 Freescale Semiconductor, MC9328MX1DVM20 Datasheet - Page 70

• Manufacturer Part Number: MC9328MX1DVM20
• Description: IC MCU I.MX 200MHZ 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX1r

Specifications of MC9328MX1DVM20

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 110
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 1.7 V ~ 3.3 V
• Oscillator Type: External
• Operating Temperature: -30°C ~ 70°C
• Package / Case: 256-MAPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -

Functional Description and Application Information
After a card receives its RCA, it switches to data transfer mode. As shown on the first diagram in
Figure
period of two Z bits (allowing time for direction switching on the bus) and then by P bits pushed up by the
responding card. The other two diagrams show the separating periods N
Figure 50
read command (which specifies the start address in the argument field). The response is sent on the
SD_CMD lines as usual. Data transmission from the card starts after the access time delay N
from the last bit of the read command. If the system is in multiple block read mode, the card sends a
continuous flow of data blocks with distance N
data stops two clock cycles after the end bit of the stop command.
70
49, SD_CMD lines in this mode are driven with push-pull drivers. The command is followed by a
shows basic read operation timing. In a read operation, the sequence starts with a single block
CMD
CMD
CMD
CMD
CMD
S T
S T
S T
Figure 49. Timing Diagrams at Data Transfer Mode
Figure 48. Timing Diagrams at Identification Mode
S T
S T
Host Command
Host Command
Content
Content
Content
Response
Host Command
Host Command
Content
Content
MC9328MX1 Technical Data, Rev. 7
CRC
CRC
CRC
Timing response end to next CMD start (data transfer mode)
CRC
CRC
E Z Z P
E Z
E Z
E Z
E Z
AC
N
N
N
Command response timing (data transfer mode)
CR
RC
CC
******
******
until the card sees a stop transmission command. The
N
N
******
Timing of command sequences (all modes)
cycles
cycles
cycles
******
******
CR
ID
cycles
cycles
P S T
Z S T
Z S T
Z S T
Z S T
Host Command
Host Command
Content
Content
Content
Identification Timing
Response
SET_RCA Timing
CID/OCR
CID/OCR
Content
Content
RC
CRC E Z Z
CRC E Z Z
CRC E Z Z
and N
Z Z
Z Z
Z
Z
CC
Z
Z
Z
Freescale Semiconductor
.
AC
, beginning