MC9328MX1DVM20 Freescale Semiconductor, MC9328MX1DVM20 Datasheet - Page 26

IC MCU I.MX 200MHZ 256-MAPBGA

MC9328MX1DVM20

Manufacturer Part Number
MC9328MX1DVM20
Description
IC MCU I.MX 200MHZ 256-MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX1r
Datasheet

Specifications of MC9328MX1DVM20

Core Processor
ARM9
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
110
Program Memory Type
ROMless
Voltage - Supply (vcc/vdd)
1.7 V ~ 3.3 V
Oscillator Type
External
Operating Temperature
-30°C ~ 70°C
Package / Case
256-MAPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Ram Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC9328MX1DVM20
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC9328MX1DVM20R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Functional Description and Application Information
4.2
Parameters of the DPLL are given in
pre-divider and T
26
DPLL input clock freq range
Pre-divider output clock
freq range
DPLL output clock freq range
Pre-divider factor (PD)
Total multiplication factor (MF)
MF integer part
MF numerator
MF denominator
Pre-multiplier lock-in time
Freq lock-in time after
full reset
Freq lock-in time after
partial reset
Phase lock-in time after
full reset
Phase lock-in time after
partial reset
Freq jitter (p-p)
Ref No.
2a
2b
3a
3b
4a
4b
1
Parameter
DPLL Timing Specifications
CLK frequency
Clock high time
Clock low time
Clock rise time
Clock fall time
Output hold time
Output setup time
dck
Parameter
is the output double clock period.
Table 9. Trace Port Timing Diagram Parameter Table
Vcc = 1.8V
Vcc = 1.8V
Vcc = 1.8V
Includes both integer and fractional parts
Should be less than the denominator
FOL mode for non-integer MF
(does not include pre-multi lock-in time)
FOL mode for non-integer MF (does not
include pre-multi lock-in time)
FPL mode and integer MF (does not include
pre-multi lock-in time)
FPL mode and integer MF (does not include
pre-multi lock-in time)
MC9328MX1 Technical Data, Rev. 7
Table
Table 10. DPLL Specifications
Minimum
Test Conditions
2.28
3.42
1.3
0
3
10. In this table, T
1.8 ± 0.1 V
Maximum
85
4
3
ref
is a reference clock period after the
Minimum
Minimum
250
220
300
270
80
5
5
0
2
2
2
3
5
1
5
0
1
3.0 ± 0.3 V
(0.01%)
Typical
(56 μs)
(50 μs)
(70 μs)
(64 μs)
0.005
280
250
350
320
Maximum
Freescale Semiconductor
100
3
3
Maximum
312.5
1022
1023
0.01
100
220
300
270
400
370
30
16
15
15
MHz
Unit
ns
ns
ns
ns
ns
ns
2•T
μ
MHz
MHz
MHz
Unit
T
T
T
T
sec
ref
ref
ref
ref
dck

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