MCF5282CVM66 Freescale Semiconductor, MCF5282CVM66 Datasheet - Page 570

• Manufacturer Part Number: MCF5282CVM66
• Description: IC MPU 512K 66MHZ 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5282CVM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 150
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Controller Family/series: ColdFire
• No. Of I/o's: 150
• Ram Memory Size: 64KB
• Cpu Speed: 66.67MHz
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of Pwm Channels: 8
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Queued Analog-to-Digital Converter (QADC)
28.7.3.2 Conversion Cycle Times
Total conversion time is made up of initial sample time, final sample time, and resolution time. Initial
sample time refers to the time during which the selected input channel is coupled through the sample buffer
amplifier to the sample capacitor. The sample buffer is used to quickly reproduce its input signal on the
sample capacitor and minimize charge sharing errors. During the final sampling period the amplifier is
bypassed, and the multiplexer input charges the sample capacitor array directly for improved accuracy.
During the resolution period, the voltage in the sample capacitor is converted to a digital value and stored
in the SAR as shown in
Initial sample time is fixed at two QCLK cycles. Final sample time can be 2, 4, 8, or 16 QCLK cycles,
depending on the value of the IST field in the CCW. Resolution time is 10 QCLK cycles.
A conversion requires a minimum of 14 QCLK cycles (7 μs with a 2.0-MHz QCLK). If the maximum final
sample time period of 16 QCLKs is selected, the total conversion time is 28 QCLKs or 14 μs (with a
2.0-MHz QCLK).
28-32
PQA4
PQA0
PQB3
PQB0
V
V
V
V
DDA
SSA
RH
RL
10-bit A/D Converter
Analog
Power
Figure
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Figure 28-19. QADC Analog Subsystem Block Diagram
28-20.
16
Chan. Decode & MUX
Compar-
ator
Sample
Buffer
16:1
Input
CSAMP
10
Approximation
Internal
Channel
Decode
Successive
State Machine & Logic
4
Register
10
6
SAR Timing
Bias Circuit
Power-
Down
10
2
Freescale Semiconductor
SAR[9:0]
CHAN[5:0]
STOP
RST
QCLK
IST
Start Conv
End OF Conv