MCF5282CVM66 Freescale Semiconductor, MCF5282CVM66 Datasheet - Page 250

• Manufacturer Part Number: MCF5282CVM66
• Description: IC MPU 512K 66MHZ 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5282CVM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 150
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Controller Family/series: ColdFire
• No. Of I/o's: 150
• Ram Memory Size: 64KB
• Cpu Speed: 66.67MHz
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of Pwm Channels: 8
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Signal Descriptions
14-10
JTAG_EN
OE
VDDPLL
VDD
PST[3:0]
VRH, VRL
VDDA, VSSA
QADC analog supply
QSPI_CLK
QSPI_CS[3:0]
QSPI_DIN
QSPI_DOUT
R/W
RCON
RSTI
RSTO
SCAS
SCKE
SCL
SDA
SDRAM_CS[1:0]
SIZ[1:0]
SRAS
VSTBY
SYNCA/SYNCB
TA
TEA
Abbreviation
Table 14-2. MCF5282 Alphabetical Signal Index (continued)
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Selects between multiplexed debug module and JTAG signals at
reset.
Indicates when an external device can drive data on the bus.
Isolate the PLL analog circuitry from digital power supply noise.
Supplies positive power to the core logic and I/O pads.
Indicate core status.
High (VRH) and low (VRL) reference potentials for the analog
converter.
Isolate the QADC analog circuitry from digital power supply
noise.
Supplies positive power to the ESD structures in the QADC
pads.
Provides the serial clock from the QSPI.
Provide QSPI peripheral chip selects.
Provides serial data to the QSPI.
Provides serial data from the QSPI.
Indicates the direction of the data transfer on the bus.
Reset configuration select.
Asserted to enter reset exception processing.
Automatically asserted with RSTI. Negation indicates that the
PLL has regained its lock.
SDRAM synchronous column address strobe.
SDRAM clock enable.
Clock signal for the I
Data input/output for the I
Interface to the chip-select lines of the SDRAMs within a
memory block.
Specify the data access size of the current external bus
reference.
SDRAM synchronous row address strobe.
Provides standby voltage to RAM array if VDD is lost.
Clear the timer’s clock, providing a means of synchronization to
externally clocked or timed events.
Indicates that the external data transfer is complete and should
be asserted for one CLKOUT cycle.
Indicates that an error condition exists for the bus transfer.
2
C interface.
2
C interface.
Function
Freescale Semiconductor
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I