MCF5274CVM166 Freescale Semiconductor, MCF5274CVM166 Datasheet - Page 3

IC MPU 32BIT 166MHZ 256-MAPBGA

MCF5274CVM166

Manufacturer Part Number
MCF5274CVM166
Description
IC MPU 32BIT 166MHZ 256-MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Datasheet

Specifications of MCF5274CVM166

Core Processor
Coldfire V2
Core Size
32-Bit
Speed
166MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
Peripherals
DMA, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Embedded Interface Type
I2C, SPI, USB, UART
Digital Ic Case Style
BGA
No. Of Pins
256
Operating Temperature Range
-40°C To +85°C
Processor Type
68K/ColdFire V2
Rohs Compliant
Yes
Family Name
MCF5xxx
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
166MHz
Instruction Set Architecture
RISC
Operating Supply Voltage (max)
1.6V
Operating Supply Voltage (min)
1.4V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
256
Package Type
MA-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MCF5274CVM166
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MCF5274CVM166
Quantity:
450
2
The superset device in the MCF5275 family comes in a 256 Mold Array Plastic Ball Grid Array
(MAPBGA) package.
3
For a detailed feature list see the MCF5275 Reference Manual (MCF5275RM).
Freescale Semiconductor
(To/From PADI)
(To/From PADI)
(To/From
JTAG
(To/From
TAP
PADI)
MDHA
PADI)
(To/From PADI)
Cryptography
Block Diagram
Features
Modules
RNGA
JTAG_EN
FAST ETHERNET
DREQ[1:0]
FAST ETHERNET
CONTROLLER
CONTROLLER
(FEC1)
(FEC0)
4 CH DMA
4 CH PWM
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 4
SKHA
Watchdog
Timer
Figure 1
DACK[3:0]
(To/From PADI)
Full Speed
USB 2.0
shows a top-level block diagram of the MCF5275, the superset device.
(To/From SRAM backdoor)
Figure 1. MCF5275 Block Diagram
Arbiter
(To/From INTC)
UART
(To/From Arbiter backdoor)
Edge
0
Port
DTIM
0
UART
(8Kx16)x4
64 Kbytes
1
SRAM
CLKGEN
V2 ColdFire CPU
DTIM
PLL
1
UART
DIV
2
INTC0
DTIM
2
I
2
16 Kbytes
(1Kx32)x4
C
PIT0
CACHE
EMAC
INTC1
DTIM
3
QSPI
PIT1
SELECTS
CHIP
PORTS
SDRAMC
(GPIO)
EIM
EBI
PIT2
CIM
Block Diagram
PIT3
D[31:16]
A[23:0]
TA
DDR
QSPI
I2C_SDA
TXDx
DTOUTx
PWMx
R/W
CS[3:0]
I2C_SCL
RXDx
DTINx
FEC0
FEC1
TRST
TSIZ[1:0]
BS[3:2]
RTSx
CTSx
USB
JTAG_EN
TMS
TDI
TEA
TCLK
TDO
3

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