DSP56311VL150 Freescale Semiconductor, DSP56311VL150 Datasheet - Page 53

• Manufacturer Part Number: DSP56311VL150
• Description: IC DSP 24BIT FIXED POINT 196-BGA
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of DSP56311VL150

• Interface: Host Interface, SSI, SCI
• Clock Rate: 150MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 384kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.80V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 196-MAPBGA
• Package: 196MA-BGA
• Numeric And Arithmetic Format: Fixed-Point
• Maximum Speed: 150 MHz
• Ram Size: 384 KB
• Device Million Instructions Per Second: 150 MIPS
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
Notes:
No.
451
452
453
454
455
456
457
458
459
460
461
462
TXC rising edge to FST out (word-length) low
TXC rising edge to data out enable from high impedance
TXC rising edge to transmitter 0 drive enable assertion
TXC rising edge to data out valid
TXC rising edge to data out high impedance
TXC rising edge to transmitter 0 drive enable deassertion
FST input (bl, wr)
FST input (wl)
FST input (wl) to transmitter 0 drive enable assertion
FST input (wl)
FST input hold time after TXC falling edge
Flag output valid after TXC rising edge
1.
2.
3.
4.
5.
6.
For the internal clock, the external clock cycle is defined by the instruction cycle time (timing 7 in Table 2-5 on page 2-6) and
the ESSI Control Register.
The word-length-relative frame sync signal waveform operates the same way as the bit-length frame sync signal waveform,
but spreads from one serial clock before the first bit clock (same as the Bit Length Frame Sync signal) until the one before last
bit clock of the first word in the frame.
Periodically sampled and not 100 percent tested
V
TXC (SCK Pin) = transmit clock
RXC (SC0 or SCK pin) = receive clock
FST (SC2 pin) = transmit frame sync
FSR (SC1 or SC2 pin) receive frame sync
i ck = Internal Clock; x ck = external clock
i ck a = internal clock, Asynchronous mode (asynchronous implies that TXC and RXC are two different clocks)
i ck s = internal clock, Synchronous mode (synchronous implies that TXC and RXC are the same clock)
bl = bit length
wl = word length
wr = word length relative
CCQH
6
6
= 3.3 V ± 0.3 V, V
to data out enable from high impedance
set-up time before TXC falling edge
6
set-up time before TXC falling edge
Characteristics
CC
= 1.8 V ± 0.1 V; T
Table 2-16.
4, 6
DSP56311 Technical Data, Rev. 8
3
J
= –40°C to +100 °C, C
2
ESSI Timings (Continued)
3
Symbol
L
= 50 pF.
35 + 0.5 × T
Expression
C
AC Electrical Characteristics
Min
21.0
21.0
2.5
2.0
4.0
0.0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
150 MHz
Max
31.0
17.0
31.0
17.0
34.0
20.0
38.4
21.0
31.0
16.0
34.0
20.0
27.0
31.0
32.0
18.0
—
—
—
—
—
—
Cond-
ition
x ck
x ck
x ck
x ck
x ck
x ck
x ck
x ck
x ck
x ck
i ck
i ck
i ck
i ck
i ck
i ck
i ck
i ck
i ck
i ck
—
—
5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2-33