XRT91L31IQ-F Exar Corporation, XRT91L31IQ-F Datasheet - Page 28

• Manufacturer Part Number: XRT91L31IQ-F
• Description: IC TXRX SONET/SDH 8BIT 64QFP
• Manufacturer: Exar Corporation
• Type: Transceiverr

Specifications of XRT91L31IQ-F

• Package / Case: 64-QFP
• Input: LVCMOS, LVPECL, LVTTL
• Output: LVCMOS, LVPECL, LVTTL
• Frequency - Max: 77.76MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Frequency-max: 77.76MHz
• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 155.52 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 240 mA or 270 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 1016-1361

XRT91L31
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
The clock synthesizer uses a 77.76 MHz or a 19.44 MHz reference clock to generate the 622.08 MHz (for STS-
12/STM-4) or 155.52 MHz (for STS-3/STM-1) SONET/SDH transmit serial data rate frequency. Differential
LVPECL input REFCLKP/N accepts a clock reference of 77.76 MHz or 19.44 MHz to synthesize a high speed
622.08 MHz clock for STS-12/STM-4 or 155.52 MHz clock for STS-3/STM-1 applications. Optionally, if a
Differential LVPECL clock source is not available, TTLREFCLK can accept an LVTTL clock signal. The clock
synthesizer uses a PLL to lock-on to the differential input REFCLKP/N or Single-Ended input TTLREFCLK
reference clock. The REFCLKP/N input should be generated from an LVPECL crystal oscillator which has a
frequency accuracy better than 20ppm in order for the transmitted data rate frequency to have the necessary
accuracy required for SONET systems. If the TTLREFCLK
reference input should be tied to a LVTTL crystal oscillator with 20ppm accuracy. The two reference clocks are
XNOR’ed and the choice between the LVPECL and LVTTL clocks are controlled tying either REFCLKP or
TTLREFCLK to ground. Table 3 shows the CMU reference clock frequency settings.
Clock Multiplier Unit requirements for reference clock.
3.6
REF
REF
REF
REF
N
Jitter specification is defined using a 12kHz to 1.3/5MHz LP-HP single-pole filter.
1
2
These reference clock jitter limits are required for the outputs to meet SONET system level jitter
Required to meet SONET output frequency stability requirements.
AME
DUTY
requirements (<10 mUI
TOL
JIT
JIT
Clock Multiplier Unit (CMU) and Re-Timer
T
ABLE
Reference clock jitter (rms) with 19.44 MHz reference
Reference clock jitter (rms) with 77.76 MHz reference
16: C
Reference clock frequency tolerance
rms
LOCK
Reference clock duty cycle
).
M
ULTIPLIER
P
ARAMETER
U
NIT REQUIREMENTS FOR REFERENCE CLOCK
28
2
reference clock is used, the TTLREFCLK
1
1
M
-20
40
IN
Table 16
T
YP
M
+20
60
13
5
specifies the
AX
REV. 1.0.2
U
ppm
NITS
ps
ps
%