XRT91L31IQ-F Exar Corporation, XRT91L31IQ-F Datasheet - Page 22

IC TXRX SONET/SDH 8BIT 64QFP

XRT91L31IQ-F

Manufacturer Part Number
XRT91L31IQ-F
Description
IC TXRX SONET/SDH 8BIT 64QFP
Manufacturer
Exar Corporation
Type
Transceiverr
Datasheet

Specifications of XRT91L31IQ-F

Package / Case
64-QFP
Input
LVCMOS, LVPECL, LVTTL
Output
LVCMOS, LVPECL, LVTTL
Frequency - Max
77.76MHz
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Frequency-max
77.76MHz
Product
Framer
Number Of Transceivers
1
Data Rate
155.52 Mbps
Supply Voltage (max)
3.465 V
Supply Voltage (min)
3.135 V
Supply Current (max)
240 mA or 270 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
1016-1361

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XRT91L31IQ-F
Manufacturer:
PHILIPS
Quantity:
23
Part Number:
XRT91L31IQ-F
Manufacturer:
Exar Corporation
Quantity:
10 000
Part Number:
XRT91L31IQ-F
Manufacturer:
EXAR/艾科嘉
Quantity:
20 000
XRT91L31
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
The receive parallel data output from the STS-12/STM-4 or STS-3/STM-1 receiver will adhere to the setup and
hold times shown in
specifications.
F
2.10
IGURE
t
t
t
t
RXDO_VALID
RXDO_VALID
PULSE_WID
PULSE_WID
t
t
S
RXPCLKO
S
RXPCLKO
t
t
10. R
RXCLK
RXCLK
YMBOL
YMBOL
Receive Parallel Data Output Timing
FRAMEPULSE
ECEIVE
RXDO[7:0]
RXPCLKO
T
T
ABLE
ABLE
RXIP
RXIN
P
Figure 10 ,Table
9: R
10: R
ARALLEL
Time the data is valid on RXDO[7:0] and FRAMEPULSE
Time the data is valid on RXDO[7:0] and FRAMEPULSE
Pulse width of frame detection pulse on FRAMEPULSE
Pulse width of frame detection pulse on FRAMEPULSE
A1
ECEIVE
ECEIVE
Receive parallel data output byte clock period
Receive parallel data output byte clock period
before and after the rising edge of RXPCLKO
before and after the rising edge of RXPCLKO
Receive high-speed serial clock period
Receive high-speed serial clock period
O
UTPUT
P
P
ARALLEL
ARALLEL
t
RXCLK
T
9, and
A2
IMING
P
P
D
ARAMETER
ARAMETER
t
RXPCLKO
D
ATA
ATA
Table
O
O
UTPUT
UTPUT
22
10.
A2
Table 11
T
T
IMING
IMING
t
t
RXDO_VALID
(STS-12/STM-4 O
PULSE_WID
(STS-3/STM-1 O
shows the PECL and TTL output timing
A2
M
M
22
4
IN
IN
A2
PERATION
PERATION
1.608
12.86
12.86
6.43
51.44
51.44
T
T
YP
YP
)
)
M
M
AX
AX
REV. 1.0.2
ns
ns
ns
ns
ns
ns
ns
ns
U
U
NITS
NITS

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