USBLC6-2SC6 STMicroelectronics, USBLC6-2SC6 Datasheet - Page 4

• Manufacturer Part Number: USBLC6-2SC6
• Description: IC ESD PROTECTION LO CAP SOT23-6
• Manufacturer: STMicroelectronics

Specifications of USBLC6-2SC6

• Voltage - Working: 5V
• Voltage - Clamping: 6V
• Technology: Mixed Technology
• Number Of Circuits: 2
• Applications: USB
• Package / Case: SOT-23-6
• Polarity: Bidirectional
• Channels: 2 Channels
• Clamping Voltage: 17 V
• Operating Voltage: 5 V
• Breakdown Voltage: 6 V
• Termination Style: SMD/SMT
• Peak Surge Current: 5 A
• Capacitance: 3.5 pF
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Dimensions: 1.75 (Max) mm W x 3.05 (Max) mm L
• Diode Type: Low Capacitance / ESD Protection
• Clamping Voltage Vc Max: 17V
• Diode Case Style: SOT-23
• No. Of Pins: 6
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 497-5235-2; USBLC6-2SC6

Technical information
2
2.1
Note:
2.2
4/14
Technical information
Surge protection
The USBLC6-2 is particularly optimized to perform surge protection based on the rail to rail
topology.
The clamping voltage V
with: V
(V
and V
Calculation example
We assume that the value of the dynamic resistance of the clamping diode is typically:
We assume that the value of the dynamic resistance of the transil diode is typically:
For an IEC 61000-4-2 surge Level 4 (Contact Discharge: V
V
So, we find:
The calculations do not take into account phenomena due to parasitic inductances.
Surge protection application example
If we consider that the connections from the pin V
GND to PCB GND plane are done by tracks of 10 mm long and 0.5 mm large, we assume
that the parasitic inductances L
an IEC 61000-4-2 surge occurs on data line, due to the rise time of this spike (t
voltage V
The dI/dt is calculated as:
The overvoltage due to the parasitic inductances is:
By taking into account the effect of these parasitic inductances due to unsuitable layout, the
clamping voltage will be :
BUS
F
forward drop voltage) / (V
V
V
R
R
I
V
V
dI/dt = I
L
V
V
p
= +5 V, and if in first approximation, we assume that :
TRANSIL
I/O
CL
CL
CL
CL
CL
CL
d
d_TRANSIL
F
= V
= 0.5
.dl/dt = L
= V
+ = V
- = - V
+ = +31.2 V
- = -13 V
+ = +31.2 + 144 + 144 = 319.2 V
- = -13.1 - 144 - 144 = -301.1 V
CL
g
T
/ R
has an extra value equal to L
p
/t
+ R
TRANSIL
= V
r
g
= 24 A/ns
F
and V
= 24 A.
= 0.5
GND
d
BR
for negative surges
.I
p
+ R
.dI/dt = 6 nH x 24 A/ns = 144 V
T
+ V
CL
= 1.1 V
d_TRANSIL
and V
F
can be calculated as follow :
for positive surges
T
BR
VBUS
forward drop threshold voltage)
= 6.1 V
.I
P
, L
I/O
and L
I/O
.dl/dt+L
GND
BUS
GND
of these tracks are about 6 nH. So when
to V
.dI/dt.
CC
g
= 8 kV, R
, from I/O to data line and from
g
= 330 ),
r
=1ns), the
USBLC6-2