MCF54452VR266 Freescale Semiconductor, MCF54452VR266 Datasheet - Page 37

• Manufacturer Part Number: MCF54452VR266
• Description: IC MPU 32BIT 266MHZ 360TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF5445xr

Specifications of MCF54452VR266

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: I²C, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 132
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.35 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 360-TEPBGA
• Family Name: MCF5445X
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 266MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 1.65/3.6V
• Operating Supply Voltage (min): 1.35/3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 360
• Package Type: TEBGA
• Leaded Process Compatible: Yes
• Rohs Compliant: Yes
• Peak Reflow Compatible (260 C): Yes
• For Use With: M54455EVB - BOARD EVAL FOR MCF5445X
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

Freescale Semiconductor
1
2
3
4
5
Name
DS10
DS11
DS12
DS13
DS14
Timings shown are for DMCR[MTFE] = 0 (classic SPI) and DCTARn[CPHA] = 0. Data is sampled on the DSPI_SIN pin
on the odd-numbered DSPI_SCK edges and driven on the DSPI_SOUT pin on even-numbered DSPI edges.
When in master mode, the baud rate is programmable in DCTARn[DBR], DCTARn[PBR], and DCTARn[BR].
This specification assumes a 50/50 duty cycle setting. The duty cycle is programmable in DCTARn[DBR],
DCTARn[CPHA], and DCTARn[PBR].
The DSPI_PCSn to DSPI_SCK delay is programmable in DCTARn[PCSSCK] and DCTARn[CSSCK].
The DSPI_SCK to DSPI_PCSn delay is programmable in DCTARn[PASC] and DCTARn[ASC].
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
DSPI_SS active to DSPI_SOUT driven
DSPI_SS inactive to DSPI_SOUT not driven
(DCTARn[CPOL] = 1)
(DCTARn[CPOL] = 0)
DSPI_SOUT
DSPI_PCSn
Table 26. DSPI Module AC Timing Specifications
DSPI_SCK
DSPI_SCK
DSPI_SIN
Characteristic
Figure 23. DSPI Classic SPI Timing — Master Mode
MCF5445x ColdFire
DS7
First Data
DS3
First Data
DS8
®
DS6
Microprocessor Data Sheet, Rev. 6
DS2
Symbol
DS2
—
—
—
—
—
Data
Data
Min
—
—
0
2
7
Last Data
DS1
Last Data
DS5
1
(continued)
DS4
Max
10
10
—
—
—
Electrical Characteristics
Unit
ns
ns
ns
ns
ns
Notes
37