MC68711E20CFNE3 Freescale Semiconductor, MC68711E20CFNE3 Datasheet - Page 71

• Manufacturer Part Number: MC68711E20CFNE3
• Description: IC MCU 8BIT 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68711E20CFNE3

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Size: 20KB (20K x 8)
• Program Memory Type: OTP
• Eeprom Size: 512 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Processor Series: M687xx
• Core: HC11
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 3 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ILIE — Idle Line Interrupt Enable Bit
TE — Transmitter Enable Bit
RE — Receiver Enable Bit
RWU — Receiver Wakeup Control Bit
SBK — Send Break Bit
6.7.4 SCI Status Register
The SCI status register (SCSR) provides inputs to the interrupt logic circuits for generation of the SCI
system interrupt.
TDRE — Transmit Data Register Empty Flag
TC — Transmit Complete Flag
RDRF — Receive Data Register Full Flag
Freescale Semiconductor
When TE goes from 0 to 1, one unit of idle character time (logic 1) is queued as a preamble.
At least one character time of break is queued and sent each time SBK is written to 1. More than one
break may be sent if the transmitter is idle at the time the SBK bit is toggled on and off, as the baud
rate clock edge could occur between writing the 1 and writing the 0 to SBK.
This flag is set when SCDR is empty. Clear the TDRE flag by reading SCSR with TDRE set and then
writing to SCDR.
This flag is set when the transmitter is idle (no data, preamble, or break transmission in progress).
Clear the TC flag by reading SCSR with TC set and then writing to SCDR.
This flag is set if a received character is ready to be read from SCDR. Clear the RDRF flag by reading
SCSR with RDRF set and then reading SCDR.
1 = IDLE interrupts disabled
1 = SCI interrupt requested when IDLE status flag is set
0 = Transmitter disabled
1 = Transmitter enabled
0 = Receiver disabled
1 = Receiver enabled
0 = Normal SCI receiver
1 = Wakeup enabled and receiver interrupts inhibited
0 = Break generator off
1 = Break codes generated as long as SBK = 1
0 = SCDR busy
1 = SCDR empty
0 = Transmitter busy
1 = Transmitter idle
0 = SCDR empty
1 = SCDR full
Address:
Reset:
Read:
Write:
$002E
TDRE
Bit 7
1
Figure 6-6. SCI Status Register (SCSR)
TC
6
1
MC68HC711D3 Data Sheet, Rev. 2.1
RDRF
5
0
IDLE
4
0
OR
3
0
NF
2
0
FE
1
0
Bit 0
0
0
SCI Registers
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